Motorola MC68HC908AB32 Technical Data Manual Download Page 194

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Timer Interface Module A (TIMA)

Technical Data

MC68HC908AB32

—

Rev. 1.0

194

Timer Interface Module A (TIMA)

MOTOROLA

Address:

$0030

Bit 7

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

Figure 11-20. TIMA Channel 3 Register High (TACH3H)

Address:

$0031

Bit 7

Bit 0

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

Figure 11-21. TIMA Channel 3 Register Low (TACH3L)

Summary of Contents for MC68HC908AB32

Page 1: ...MC68HC908AB32 D REV 1 0 MC68HC908AB32 HCMOS Microcontroller Unit TECHNICAL DATA ...

Page 2: ......

Page 3: ...9 Section 8 System Integration Module SIM 109 Section 9 Clock Generator Module CGM 131 Section 10 Monitor ROM MON 157 Section 11 Timer Interface Module A TIMA 169 Section 12 Timer Interface Module B TIMB 195 Section 13 Programmable Interrupt Timer PIT 221 Section 14 Analog to Digital Converter ADC 229 Section 15 Serial Communications Interface Module SCI 239 Section 16 Serial Peripheral Interface ...

Page 4: ...st of Sections MOTOROLA Section 20 Computer Operating Properly COP 353 Section 21 Low Voltage Inhibit LVI 359 Section 22 Break Module BRK 365 Section 23 Electrical Specifications 373 Section 24 Mechanical Specifications 387 Section 25 Ordering Information 389 ...

Page 5: ...y Pin VDDA 35 1 6 6 Analog Ground Pin VSSA 35 1 6 7 Analog Ground Pin AVSS VREFL 35 1 6 8 ADC Voltage Reference Pin VREFH 36 1 6 9 Analog Supply Pin VDDAREF 36 1 6 10 External Filter Capacitor Pin CGMXFC 36 1 6 11 Port A Input Output I O Pins PTA7 PTA0 36 1 6 12 Port B I O Pins PTB7 ATD7 PTB0 ATD0 36 1 6 13 Port C I O Pins PTC5 PTC0 36 1 6 14 Port D I O Pins PTD7 PTD0 37 1 6 15 Port E I O Pins PTE...

Page 6: ...Access Memory RAM 3 1 Contents 57 3 2 Introduction 57 3 3 Functional Description 57 Section 4 FLASH Memory 4 1 Contents 59 4 2 Introduction 59 4 3 Functional Description 59 4 4 FLASH Control Register 60 4 5 FLASH Page Erase Operation 61 4 6 FLASH Mass Erase Operation 62 4 7 FLASH Program Read Operation 63 4 8 FLASH Block Protection 64 4 8 1 FLASH Block Protect Register 66 4 9 Wait Mode 67 4 10 Sto...

Page 7: ...wer Modes 76 5 10 1 Wait Mode 76 5 10 2 Stop Mode 77 5 11 EEPROM Registers 77 5 11 1 EEPROM Control Register 77 5 11 2 EEPROM Array Configuration Register 79 5 11 2 1 EEPROM Non Volatile Register 80 5 11 3 EEPROM Timebase Divider Register 80 5 11 3 1 EEPROM Timebase Divider Non Volatile Register 82 Section 6 Configuration Register CONFIG 6 1 Contents 85 6 2 Introduction 85 6 3 Functional descripti...

Page 8: ...SIM 8 1 Contents 109 8 2 Introduction 110 8 3 SIM Bus Clock Control and Generation 112 8 3 1 Bus Timing 113 8 3 2 Clock Start Up from POR or LVI Reset 113 8 3 3 Clocks in Stop and Wait Modes 113 8 4 Reset and System Initialization 113 8 4 1 External Pin Reset 114 8 4 2 Active Resets from Internal Sources 114 8 4 2 1 Power On Reset 115 8 4 2 2 Computer Operating Properly COP Reset 116 8 4 2 3 Illeg...

Page 9: ...egister 129 Section 9 Clock Generator Module CGM 9 1 Contents 131 9 2 Introduction 132 9 3 Features 132 9 4 Functional Description 133 9 4 1 Crystal Oscillator Circuit 134 9 4 2 Phase Locked Loop PLL Circuit 135 9 4 2 1 PLL Circuits 135 9 4 2 2 Acquisition and Tracking Modes 136 9 4 2 3 Manual and Automatic PLL Bandwidth Modes 136 9 4 2 4 Programming the PLL 138 9 4 2 5 Special Programming Excepti...

Page 10: ... 8 Low Power Modes 150 9 8 1 Wait Mode 150 9 8 2 Stop Mode 151 9 9 CGM During Break Interrupts 151 9 10 Acquisition Lock Time Specifications 151 9 10 1 Acquisition Lock Time Definitions 152 9 10 2 Parametric Influences On Reaction Time 153 9 10 3 Choosing a Filter Capacitor 154 9 10 4 Reaction Time Calculation 155 Section 10 Monitor ROM MON 10 1 Contents 157 10 2 Introduction 157 10 3 Features 158...

Page 11: ... 176 11 5 4 Pulse Width Modulation PWM 177 11 5 4 1 Unbuffered PWM Signal Generation 178 11 5 4 2 Buffered PWM Signal Generation 179 11 5 4 3 PWM Initialization 180 11 6 Interrupts 181 11 7 Low Power Modes 181 11 7 1 Wait Mode 182 11 7 2 Stop Mode 182 11 8 TIMA During Break Interrupts 182 11 9 I O Signals 183 11 9 1 TIMA Clock Pin 183 11 9 2 TIMA Channel I O Pins 183 11 10 I O Registers 184 11 10 ...

Page 12: ... 202 12 5 4 Pulse Width Modulation PWM 203 12 5 4 1 Unbuffered PWM Signal Generation 204 12 5 4 2 Buffered PWM Signal Generation 205 12 5 4 3 PWM Initialization 206 12 6 Interrupts 207 12 7 Low Power Modes 207 12 7 1 Wait Mode 208 12 7 2 Stop Mode 208 12 8 TIMB During Break Interrupts 208 12 9 I O Signals 209 12 9 1 TIMB Clock Pin 209 12 9 2 TIMB Channel I O Pins 209 12 10 I O Registers 210 12 10 ...

Page 13: ... 7 I O Registers 225 13 7 1 PIT Status and Control Register 225 13 7 2 PIT Counter Registers 227 13 7 3 PIT Counter Modulo Registers 228 Section 14 Analog to Digital Converter ADC 14 1 Contents 229 14 2 Introduction 230 14 3 Features 230 14 4 Functional Description 231 14 4 1 ADC Port I O Pins 232 14 4 2 Voltage Conversion 232 14 4 3 Conversion Time 232 14 4 4 Conversion 232 14 4 5 Accuracy and Pr...

Page 14: ...40 15 3 Features 240 15 4 Pin Name Conventions 242 15 5 Functional Description 242 15 5 1 Data Format 245 15 5 2 Transmitter 245 15 5 2 1 Character Length 247 15 5 2 2 Character Transmission 247 15 5 2 3 Break Characters 248 15 5 2 4 Idle Characters 248 15 5 2 5 Inversion of Transmitted Output 249 15 5 2 6 Transmitter Interrupts 249 15 5 3 Receiver 250 15 5 3 1 Character Length 250 15 5 3 2 Charac...

Page 15: ... SCI Data Register 274 15 9 7 SCI Baud Rate Register 275 Section 16 Serial Peripheral Interface Module SPI 16 1 Contents 279 16 2 Introduction 280 16 3 Features 280 16 4 Pin Name Conventions and I O Register Addresses 281 16 5 Functional Description 281 16 5 1 Master Mode 283 16 5 2 Slave Mode 284 16 6 Transmission Formats 285 16 6 1 Clock Phase and Polarity Controls 285 16 6 2 Transmission Format...

Page 16: ...isters 304 16 14 1 SPI Control Register 304 16 14 2 SPI Status and Control Register 306 16 14 3 SPI Data Register 309 Section 17 Input Output I O Ports 17 1 Contents 311 17 2 Introduction 312 17 3 Port A 316 17 3 1 Port A Data Register PTA 316 17 3 2 Data Direction Register A DDRA 316 17 4 Port B 318 17 4 1 Port B Data Register PTB 318 17 4 2 Data Direction Register B DDRB 319 17 5 Port C 320 17 5...

Page 17: ... Direction Register G DDRG 333 17 10 Port H 335 17 10 1 Port H Data Register PTH 335 17 10 2 Data Direction Register H DDRH 335 Section 18 External Interrupt IRQ 18 1 Contents 339 18 2 Introduction 339 18 3 Features 339 18 4 Functional Description 340 18 4 1 IRQ Pin 342 18 5 IRQ Status and Control Register ISCR 343 18 6 IRQ Module During Break Interrupts 344 Section 19 Keyboard Interrupt Module KB...

Page 18: ...escription 354 20 4 I O Signals 355 20 4 1 CGMXCLK 355 20 4 2 STOP Instruction 355 20 4 3 COPCTL Write 355 20 4 4 Power On Reset 355 20 4 5 Internal Reset 356 20 4 6 Reset Vector Fetch 356 20 4 7 COPD COP Disable 356 20 4 8 COPRS COP Rate Select 356 20 5 COP Control Register 357 20 6 Interrupts 357 20 7 Monitor Mode 357 20 8 Low Power Modes 357 20 8 1 Wait Mode 358 20 8 2 Stop Mode 358 20 9 COP Mo...

Page 19: ...n 365 22 3 Features 366 22 4 Functional Description 366 22 4 1 Flag Protection During Break Interrupts 368 22 4 2 CPU During Break Interrupts 368 22 4 3 PIT TIMA and TIMB During Break Interrupts 368 22 4 4 COP During Break Interrupts 368 22 5 Low Power Modes 368 22 5 1 Wait Mode 368 22 5 2 Stop Mode 369 22 6 Break Module Registers 369 22 6 1 Break Status and Control Register 369 22 6 2 Break Addre...

Page 20: ...cteristics 378 23 10 ADC Characteristics 379 23 11 SPI Characteristics 380 23 12 Clock Generation Module Characteristics 383 23 12 1 CGM Operating Conditions 383 23 12 2 CGM Component Information 383 23 12 3 CGM Acquisition Lock Time Information 384 23 13 FLASH Memory Characteristics 385 Section 24 Mechanical Specifications 24 1 Contents 387 24 2 Introduction 387 24 3 64 Pin Plastic Quad Flat Pack...

Page 21: ...ect Register FLBPR 66 5 1 EEPROM I O Register Summary 70 5 2 EEPROM Control Register EECR 77 5 3 EEPROM Array Configuration Register EEACR 79 5 4 EEPROM Non Volatile Register EENVR 80 5 5 EEPROM Divider Register High EEDIVH 81 5 6 EEPROM Divider Register Low EEDIVL 81 5 7 EEPROM Divider Non volatile Register High EEDIVHNVR 82 5 8 EEPROM Divider Non volatile Register Low EEDIVLNVR 82 6 1 Configurat...

Page 22: ...k 125 8 14 Wait Recovery from Internal Reset 125 8 15 Stop Mode Entry Timing 126 8 16 Stop Mode Recovery from Interrupt or Break 126 8 17 SIM Break Status Register SBSR 127 8 18 SIM Reset Status Register SRSR 128 8 19 SIM Break Flag Control Register SBFCR 129 9 1 CGM Block Diagram 133 9 2 CGM I O Register Summary 134 9 3 CGM External Connections 141 9 4 CGM I O Register Summary 144 9 5 PLL Control...

Page 23: ...11 16 TIMA Channel 1 Register High TACH1H 193 11 17 TIMA Channel 1 Register Low TACH1L 193 11 18 TIMA Channel 2 Register High TACH2H 193 11 19 TIMA Channel 2 Register Low TACH2L 193 11 20 TIMA Channel 3 Register High TACH3H 194 11 21 TIMA Channel 3 Register Low TACH3L 194 12 1 TIMB Block Diagram 198 12 2 TIMB I O Register Summary 199 12 3 PWM Period and Pulse Width 203 12 4 TIMB Status and Control...

Page 24: ...Counter Modulo Register High PMODH 228 13 7 PIT Counter Modulo Register Low PMODL 228 14 1 ADC Register Summary 230 14 2 ADC Block Diagram 231 14 3 ADC Status and Control Register ADSCR 235 14 4 ADC Data Register ADR 237 14 5 ADC Clock Register ADCLK 237 15 1 SCI Module Block Diagram 243 15 2 SCI I O Register Summary 244 15 3 SCI Data Formats 245 15 4 SCI Transmitter 246 15 5 SCI Receiver Block Di...

Page 25: ...304 16 14 SPI Status and Control Register SPSCR 306 16 15 SPI Data Register SPDR 309 17 1 I O Port Register Summary 312 17 2 Port A Data Register PTA 316 17 3 Data Direction Register A DDRA 316 17 4 Port A I O Circuit 317 17 5 Port B Data Register PTB 318 17 6 Data Direction Register B DDRB 319 17 7 Port B I O Circuit 319 17 8 Port C Data Register PTC 320 17 9 Data Direction Register B DDRB 321 17...

Page 26: ...rrupt Block Diagram 347 19 3 Keyboard Status and Control Register KBSCR 350 19 4 Keyboard Interrupt Enable Register KBIER 351 20 1 COP Block Diagram 354 20 2 Configuration Register 1 CONFIG1 356 20 3 COP Control Register COPCTL 357 21 1 LVI Module Block Diagram 360 21 2 LVI I O Register Summary 361 21 3 LVI Status Register LVISR 362 22 1 Break Module Block Diagram 367 22 2 Break Module I O Registe...

Page 27: ...l naming conventions 111 8 2 PIN Bit Set Timing 114 8 3 Vector Addresses 122 8 4 SIM Registers 127 9 1 VCO Frequency Multiplier N Selection 149 10 1 Monitor Mode Entry Conditions 160 10 2 Mode Differences 161 10 3 READ Read Memory Command 163 10 4 WRITE Write Memory Command 164 10 5 IREAD Indexed Read Command 164 10 6 IWRITE Indexed Write Command 165 10 7 READSP Read Stack Pointer Command 165 10 8...

Page 28: ...ormat Selection 264 15 6 SCI Baud Rate Prescaling 275 15 7 SCI Baud Rate Selection 276 15 8 SCI Baud Rate Selection Examples 277 16 1 Pin Name Conventions 281 16 2 SPI Interrupts 296 16 3 SPI Configuration 303 16 4 SPI Master Baud Rate Selection 308 17 1 Port Control Register Bits Summary 314 17 2 Port A Pin Functions 317 17 3 Port B Pin Functions 320 17 4 Port C Pin Functions 322 17 5 Port D Pin ...

Page 29: ...A 35 1 6 6 Analog Ground Pin VSSA 35 1 6 7 Analog Ground Pin AVSS VREFL 35 1 6 8 ADC Voltage Reference Pin VREFH 36 1 6 9 Analog Supply Pin VDDAREF 36 1 6 10 External Filter Capacitor Pin CGMXFC 36 1 6 11 Port A Input Output I O Pins PTA7 PTA0 36 1 6 12 Port B I O Pins PTB7 ATD7 PTB0 ATD0 36 1 6 13 Port C I O Pins PTC5 PTC0 36 1 6 14 Port D I O Pins PTD7 PTD0 37 1 6 15 Port E I O Pins PTE7 SPSCK P...

Page 30: ...es Memory map and pin functions compatible with MC68HC08AB32 and MC68HC08AB16 8 MHz internal bus frequency 32K bytes user program FLASH memory with security1 feature 512 bytes of on chip EEPROM with security feature 1K byte of on chip RAM Clock generator module CGM Two 16 bit 4 channel timer interface modules TIMA and TIMB with selectable input capture output compare and PWM capability on each cha...

Page 31: ...l opcode detection with optional reset Illegal address detection with optional reset 64 pin quad flat pack QFP Features of the CPU08 include the following Enhanced HC05 programming model Extensive loop control functions 16 addressing modes eight more than the HC05 16 bit Index register and stack pointer Memory to memory data transfers Fast 8 8 multiply instruction Fast 16 8 divide instruction Bina...

Page 32: ...PTA0 VREFH PTE7 SPSCK PTE6 MOSI PTE5 MISO PTE4 SS PTE3 TACH1 PTE2 TACH0 PTE1 RxD PTE0 TxD AVSS VREFL 4 CHANNEL TIMER INTERFACE MODULE A 4 9125 MHz OSCILLATOR PHASE LOCKED LOOP SERIAL COMMUNICATIONS INTERFACE MODULE POWER ON RESET MODULE POWER VSS VDD VSSA VDDA Ports are software configurable with pullup device if input port Higher current drive port pins Pin contains integrated pullup device Pullu...

Page 33: ...xD PTE2 TACH0 PTE3 TACH1 PTH0 KBD3 PTD3 PTD2 AVSS VREFL VDDAREF PTD1 PTD0 PTB6 ATD6 PTB5 ATD5 PTB4 ATD4 PTB3 ATD3 PTB2 ATD2 PTB1 ATD1 PTB0 ATD0 PTA7 V SSA V DDA VREFH PTD7 PTD6 TACLK PTD5 PTD4 TBCLK PTH1 KBD4 PTC5 PTC3 PTC2 MCLK PTC1 PTC0 OSC1 OSC2 PTE6 MOSI PTE4 SS PTE5 MISO PTE7 SPSCK V SS V DD PTG0 KBD0 PTG1 KBD1 PTG2 KBD2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1...

Page 34: ... bypassing at the MCU as Figure 1 3 shows Place the C1 bypass capacitor as close to the MCU as possible Use a high frequency response ceramic capacitor for C1 C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels Figure 1 3 Power Supply Bypassing VSS is also the ground for the port output buffers and the ground return for t...

Page 35: ...m Integration Module SIM 1 6 4 External Interrupt Pin IRQ IRQ is an asynchronous external interrupt pin This pin contains an internal pullup resistor See Section 18 External Interrupt IRQ 1 6 5 Analog Power Supply Pin VDDA VDDA is the power supply pin for the clock generator module CGM 1 6 6 Analog Ground Pin VSSA The VSSA analog ground pin is used only for the ground connections for the clock gen...

Page 36: ...ction for the CGM See Section 9 Clock Generator Module CGM 1 6 11 Port A Input Output I O Pins PTA7 PTA0 PTA7 PTA0 are general purpose bidirectional I O port pins See Section 17 Input Output I O Ports 1 6 12 Port B I O Pins PTB7 ATD7 PTB0 ATD0 PTB7 PTB0 are special function bidirectional port pins PTB7 PTB0 are shared with the analog to digital convertor ADC input pins ATD7 ATD0 See Section 14 Ana...

Page 37: ...Module SCI Section 16 Serial Peripheral Interface Module SPI Section 11 Timer Interface Module A TIMA and Section 17 Input Output I O Ports 1 6 16 Port F I O Pins PTF7 PTF0 TACH2 PTF7 PTF6 are general purpose bidirectional I O port pins PTF5 PTF0 are special function bidirectional port pins PTF5 PTF2 are shared with timer B TIMB and PTF1 PTF0 are shared with timer A TIMA See Section 11 Timer Inter...

Page 38: ...Hi Z PTD4 TBCLK General purpose I O Timer external input clock Dual State No Input Hi Z PTD3 PTD0 General purpose I O Dual State No Input Hi Z PTE7 SPSCK General purpose I O SPI clock Dual State open drain Yes Input Hi Z PTE6 MOSI General purpose I O SPI data path Dual State open drain Yes Input Hi Z PTE5 MISO General purpose I O SPI data path Dual State open drain Yes Input Hi Z PTE4 SS General p...

Page 39: ...2 General purpose I O Timer A channel 2 Dual State Yes Input Hi Z PTG2 KBD2 PTG0 KBD0 General purpose I O with key wakeup feature Dual State Yes Input Hi Z PTH1 KBD4 PTH0 KBD3 General purpose I O with key wakeup feature Dual State Yes Input Hi Z VDD Logical chip power supply NA NA NA VSS Logical chip ground NA NA NA VDDA Analog power supply CGM NA NA NA VSSA Analog ground CGM NA NA NA VREFH ADC re...

Page 40: ...ck output from CGM module Bus clock CGMOUT divided by two SPSCK SPI serial clock see 16 13 3 SPSCK Serial Clock TACLK External clock input for TIMA see 11 9 1 TIMA Clock Pin TBCLK External clock input for TIMB see 12 9 1 TIMB Clock Pin Table 1 3 Clock Source Summary Module Clock Source ADC CGMXCLK or bus clock COP CGMXCLK CPU Bus clock EEPROM CGMXCLK or bus clock ROM Bus clock RAM Bus clock SPI SP...

Page 41: ... address 64K bytes of memory space The memory map shown in Figure 2 1 includes 32 256 bytes of user FLASH memory 512 bytes of EEPROM 1024 bytes of random access memory RAM 48 bytes of user defined vectors 307 bytes of monitor ROM 2 3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled In the memory map Figure 2...

Page 42: ...us register SRSR FE03 SIM break flag control register SBFCR FE08 FLASH control register FLCR FE0C break address register high BRKH FE0D break address register low BRKL FE0E break status and control register BRKSCR FE0F LVI status register LVISR FE10 EEPROM divider non volatile register high EEDIVHNVR FE11 EEPROM divider non volatile register low EEDIVLNVR FE1A EEPROM timebase divider register high...

Page 43: ...tes 04FF 0500 Reserved 128 Bytes 057F 0580 Unimplemented 640 Bytes 07FF 0800 EEPROM 512 Bytes 09FF 0A00 Unimplemented 30 208 Bytes 7FFF 8000 FLASH Memory 32 256 Bytes FDFF FE00 SIM Break Status Register SBSR FE01 SIM Reset Status Register SRSR FE02 Reserved FE03 SIM Break Flag Control Register SBFCR FE04 FE07 Reserved 4 Bytes FE08 FLASH Control Register FLCR Figure 2 1 Memory Map ...

Page 44: ...IVLNVR FE12 FE19 Reserved 8 Bytes FE1A EEPROM Timebase Divider Register High EEDIVH FE1B EEPROM Timebase Divider Register Low EEDIVL FE1C EEPROM Non volatile Register EENVR FE1D EEPROM Control Register EECR FE1E Reserved FE1F EEPROM Array Configuration Register EEACR FE20 Monitor ROM 307 Bytes FF52 FF53 Unimplemented 43 Bytes FF7D FF7E FLASH Block Protect Register FLBPR FF7F Unimplemented 65 Bytes...

Page 45: ...0004 Data Direction Register A DDRA Read DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write Reset 0 0 0 0 0 0 0 0 0005 Data Direction Register B DDRB Read DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write Reset 0 0 0 0 0 0 0 0 0006 Data Direction Register C DDRC Read MCLKEN 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write Reset 0 0 0 0 0 0 0 0 0007 Data Direction Register D DDRD Read DDRD7 DDRD6...

Page 46: ... Read 0 0 0 0 0 DDRG2 DDRG1 DDRG0 Write Reset 0 0 0 0 0 0 0 0 000F Data Direction Register H DDRH Read 0 0 0 0 0 0 DDRH1 DDRH0 Write Reset 0 0 0 0 0 0 0 0 0010 SPI Control Register SPCR Read SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Reset 0 0 1 0 1 0 0 0 0011 SPI Status and Control Register SPSCR Read SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0 Write Reset 0 0 0 0 1 0 0 0 0012 SPI Data Registe...

Page 47: ... Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6 T5 T4 T3 T2 T1 T0 Reset Unaffected by reset 0019 SCI Baud Rate Register SCBR Read 0 0 SCP1 SCP0 R SCR2 SCR1 SCR0 Write Reset 0 0 0 0 0 0 0 0 001A IRQ Status and Control Register ISCR Read 0 0 0 0 IRQF 0 IMASK MODE Write ACK Reset 0 0 0 0 0 0 0 0 001B Keyboard Status and Control Register KBSCR Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 ...

Page 48: ...Counter Register High TACNTH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 0023 Timer A Counter Register Low TACNTL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 0024 Timer A Counter Modulo Register High TAMODH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 0025 Timer A Counter Modulo Register Low TAMODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1...

Page 49: ... Register TASC2 Read CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX Write 0 Reset 0 0 0 0 0 0 0 0 002D Timer A Channel 2 Register High TACH2H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 002E Timer A Channel 2 Register Low TACH2L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 002F Timer A Channel 3 Status and Control Register TASC3 Read CH3F CH3IE 0 MS...

Page 50: ...0 0 0 0 0 0036 Timer B Channel 3 Register High TACH3H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 0037 Timer B Channel 3 Register Low TBCH3L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 0038 Analog to Digital Status and Control Register ADSCR Read COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write Reset 0 0 0 1 1 1 1 1 0039 Analog to Digital Data ...

Page 51: ...nd Control Register TBSC Read TOF TOIE TSTOP 0 0 PS2 PS1 PS0 Write 0 TRST Reset 0 0 1 0 0 0 0 0 0041 Timer B Counter Register High TBCNTH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 0042 Timer B Counter Register Low TBCNTL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 0043 Timer B Counter Modulo Register High TBMODH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1...

Page 52: ...004A Timer B Channel 1 Register Low TBCH1L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 004B PIT Status and Control Register PSC Read POF POIE PSTOP 0 0 PPS2 PPS1 PPS0 Write 0 PRST Reset 0 0 1 0 0 0 0 0 004C PIT Counter Register High PCNTH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 004D PIT Counter Register Low PCNTL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Rese...

Page 53: ...te Reset 0 0 0 0 0 0 0 0 FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write Reset 0 FE04 Reserved Read R R R R R R R R Write Reset FE05 Reserved Read R R R R R R R R Write Reset FE06 Reserved Read R R R R R R R R Write Reset FE07 Reserved Read R R R R R R R R Write Reset FE08 FLASH Control Register FLCR Read 0 0 0 0 HVEN MASS ERASE PGM Write Reset 0 0 0 0 0 0 0 0 FE09 Reserve...

Page 54: ...et 0 0 0 0 0 0 0 0 FE10 EEDIV Non volatile Register High EEDIVHNVR Read EEDIVSECD R R R R EEDIV10 EEDIV9 EEDIV8 Write Reset Unaffected by reset FF when blank FE11 EEDIV Non volatile Register Low EEDIVLNVR Read EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Write Reset Unaffected by reset FF when blank Non volatile FLASH register write by programming FE1A EE Divider Register High EEDIVH Re...

Page 55: ...R R R Write Reset FE1F EEPROM Array Configuration Register EEACR Read CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write Reset Contents of EENVR FE1C FF7E FLASH Block Protect Register FLBPR Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write Reset Unaffected by reset Non volatile FLASH register write by programming FFFF COP Control Register COPCTL Read Low byte of reset vector Write Writing clear...

Page 56: ...nsmit Vector Low FFE4 SPI Receive Vector High FFE5 SPI Receive Vector Low FFE6 Timer B Overflow Vector High FFE7 Timer B Overflow Vector Low FFE8 Timer B Channel 1 Vector High FFE9 Timer B Channel 1 Vector Low FFEA Timer B Channel 0 Vector High FFEB Timer B Channel 0 Vector Low FFEC Timer A Overflow Vector High FFED Timer A Overflow Vector Low FFEE Timer A Channel 3 Vector High FFEF Timer A Channe...

Page 57: ...y space NOTE For correct operation the stack pointer must point only to RAM locations Within page zero are 176 bytes of RAM Because the location of the stack RAM is programmable all page zero RAM locations can be used for I O control and user data or code When the stack pointer is moved from its reset location at 00FF out of page zero direct addressing mode instructions can efficiently access all ...

Page 58: ...ing a subroutine call the CPU uses two bytes of the stack to store the return address The stack pointer decrements during pushes and increments during pulls NOTE Be careful when using nested subroutines The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation ...

Page 59: ... 4 2 Introduction This section describes the operation of the embedded FLASH memory This memory can be read programmed and erased from a single external supply The program and erase operations are enabled through the use of an internal charge pump 4 3 Functional Description The FLASH memory is an array of 32 256 bytes with an additional 48 bytes of user vectors and one byte of block protection An ...

Page 60: ...nformation NOTE A security feature prevents viewing of the FLASH contents 1 4 4 FLASH Control Register The FLASH control register FLCR controls FLASH program and erase operations HVEN High Voltage Enable Bit This read write bit enables the charge pump to drive high voltages for program and erase operations in the array HVEN can only be set if either PGM 1 or ERASE 1 and the proper sequence for pro...

Page 61: ...tion unselected PGM Program Control Bit This read write bit configures the memory for program operation PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Program operation selected 0 Program operation unselected 4 5 FLASH Page Erase Operation Use this step by step procedure to erase a page 128 bytes of FLASH memory to read as logic 1 1 Se...

Page 62: ...ck protect register 3 Write any data to any FLASH address within the FLASH memory address range 4 Wait for a time tnvs min 10µs 5 Set the HVEN bit 6 Wait for a time tMErase min 4ms 7 Clear the ERASE bit 8 Wait for a time tnvhl min 100µs 9 Clear the HVEN bit 10 After a time trcv min 1µs the memory can be accessed again in read mode When in Monitor mode with security sequence failed see 10 5 Securit...

Page 63: ...ess and data for programming 2 Read from the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired 4 Wait for a time tnvs min 10µs 5 Set the HVEN bit 6 Wait for a time tpgs min 5µs 7 Write data to the FLASH address to be programmed 8 Wait for a time tPROG min 30µs 9 Repeat step 7 and 8 until all the bytes within the row are programmed 10 Clear the ...

Page 64: ...e protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory FFFF When the memory is protected the HVEN bit cannot be set in either ERASE or PROGRAM operations NOTE In performing a program or erase operation the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0 s...

Page 65: ...ss to be programmed Wait for a time tPROG Clear PGM bit Wait for a time tnvh Clear HVEN bit Wait for a time trcv Completed programming this row Y N End of programming The time between each FLASH address change step 7 to step 7 or must not exceed the maximum programming time tPROG max the time between the last FLASH address programmed to clearing PGM bit step 7 to step 10 NOTE 1 2 3 4 5 6 7 8 10 11...

Page 66: ... 0s The resultant 16 bit address is used for specifying the start address of the FLASH memory for block protection The FLASH is protected from this start address to the end of FLASH memory at FFFF With this mechanism the protect start address can be XX00 and XX80 128 bytes page boundaries within the FLASH memory Figure 4 4 FLASH Block Protect Start Address Address FF7E Bit 7 6 5 4 3 2 1 Bit 0 Read...

Page 67: ... affect the operation of the FLASH memory directly but there will not be any memory activity since the CPU is inactive The STOP instruction should not be executed while performing a program or erase operation on the FLASH otherwise the operation will discontinue and the FLASH will be on Standby Mode NOTE Standby Mode is the power saving mode of the FLASH module in which all internal control signal...

Page 68: ...FLASH Memory Technical Data MC68HC908AB32 Rev 1 0 68 FLASH Memory MOTOROLA ...

Page 69: ...9 EEPROM Programming and Erasing 73 5 9 1 EEPROM Programming 74 5 9 2 EEPROM Erasing 75 5 10 Low Power Modes 76 5 10 1 Wait Mode 76 5 10 2 Stop Mode 77 5 11 EEPROM Registers 77 5 11 1 EEPROM Control Register 77 5 11 2 EEPROM Array Configuration Register 79 5 11 2 1 EEPROM Non Volatile Register 80 5 11 3 EEPROM Timebase Divider Register 80 5 11 3 1 EEPROM Timebase Divider Non Volatile Register 82 5...

Page 70: ...et Unaffected by reset FF when blank FE1A EE Divider Register High EEDIVH Read EEDIVSECD R R R R EEDIV10 EEDIV9 EEDIV8 Write Reset Contents of EEDIVHNVR FE10 FE1B EE Divider Register Low EEDIVL Read EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Write Reset Contents of EEDIVLNVR FE11 FE1C EEPROM Non volatile Register EENVR Read CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write Reset Un...

Page 71: ... volatile register EEDIVNVR contain the default settings for the following EEPROM configurations Security option Block protection EEPROM timebase reference EENVR and EEDIVNVR are non volatile EEPROM registers They are programmed and erased in the same way as EEPROM bytes The contents of these registers are loaded into their respective volatile registers during a MCU reset The values in these read ...

Page 72: ... programmed into the EEPROM timebase divider non volatile register prior to any EEPROM program or erase operations see 5 5 EEPROM Configuration and 5 11 3 1 EEPROM Timebase Divider Non Volatile Register 5 7 EEPROM Security Options The EEPROM has a special security option enabled by programming the EEPRTCT bit to 0 in the EEPROM non volatile register EENVR Once security is enabled the following lim...

Page 73: ...one byte The erase operation changes an EEPROM bit from logic 0 to logic 1 In a single erase operation the minimum EEPROM erase size is one byte the maximum is the entire EEPROM array For each EEPROM byte the write erase endurance is 10 000 cycles One write erase cycle is defined as a maximum of eight programming operations on the same byte followed by an erase operation of the that byte Therefore...

Page 74: ...AS1 and EERAS0 must be cleared for programming Setting the EELAT bit configures the address and data buses to latch data for programming the array Only data with a valid EEPROM address will be latched If EELAT is set other writes to the EECR will be allowed after a valid EEPROM write B If more than one valid EEPROM writes occur the last address and data will be latched overriding the previous addr...

Page 75: ...Erasing changes the state to a logic 1 Only EEPROM bytes in the non protected blocks and EENVR register can be erased Use the following procedure to erase a byte block or the entire EEPROM 1 Configure EERAS1 and EERAS0 for byte block or bulk erase set EELAT in EECR A 2 Byte erase write any data to the desired address B Block erase write any data to an address within the desired block B Bulk erase ...

Page 76: ...dress is latched This is to ensure proper programming sequence Once EEPGM is set do not read any EEPROM locations otherwise the current erase cycle will be unsuccessful When EEPGM is set the erase mode cannot be changed and the on board erasing sequence will be activated D The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEBYTE tEBLOCK tEBULK However on other MCUs this dela...

Page 77: ...s to the EEPROM is only possible after the programming sequence has completed If stop mode is entered while EELAT and EEPGM is cleared the programming sequence will be terminated abruptly In either case the data integrity of the EEPROM is not guaranteed 5 11 EEPROM Registers Four I O registers and three non volatile registers control program erase and options of the EEPROM array 5 11 1 EEPROM Cont...

Page 78: ...s for programming the EEPROM array EELAT can not be cleared if EEPGM is still set Reset clears this bit 1 Buses configured for EEPROM program or erase operation 0 Buses configured for normal operation AUTO Automatic termination of program erase cycle When AUTO is set EEPGM is cleared automatically after the program erase cycle is terminated by the internal timer See note D for 5 9 1 EEPROM Program...

Page 79: ...ion will only clear EEPGM This is to allow time for the removal of high voltage 5 11 2 EEPROM Array Configuration Register The EEPROM array configuration register configures EEPROM security and EEPROM block protection This read only register is loaded with the contents of the EEPROM non volatile register EENVR after a reset CON 3 1 Unused EEPRTCT EEPROM Protection Bit The EEPRTCT bit is used to en...

Page 80: ...OTE The EENVR is factory programmed with 10 5 11 3 EEPROM Timebase Divider Register The 16 bit EEPROM timebase divider register consists of two 8 bit registers EEDIVH and EEDIVL The 11 bit value in this register is used to configure the timebase divider circuit to obtain the 35µs timebase for EEPROM control Block Number EEBPx Address Range EEBP0 0800 087F EEBP1 0880 08FF EEBP2 0900 097F EEBP3 0980...

Page 81: ...EEDIV security feature disabled 0 EEDIV security feature enabled EEDIV 10 0 EEPROM Timebase Prescaler These prescaler bits store the value of EEDIV which is used as the divisor to derive a timebase of 35µs from the selected reference clock source CGMXCLK or bus clock see 6 5 Configuration Register 2 for the EEPROM related internal timer and circuits EEDIV 10 0 bits are readable at any time They ar...

Page 82: ...t EEPROM timebase divider non volatile register consists of two 8 bit registers EEDIVHNVR and EEDIVLNVR The contents of these two registers are respectively loaded into the EEPROM timebase divider registers EEDIVH and EEDIVL after a reset These two registers are erased and programmed in the same way as an EEPROM byte Address FE10 Bit 7 6 5 4 3 2 1 Bit 0 Read EEDIVSECD R R R R EEDIV10 EEDIV9 EEDIV8...

Page 83: ... the EEDIVHNVR NOTE Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a system reset the EEDIV security feature is permanently enabled because the EEDIVSECD bit in the EEDIVH is always loaded with a 0 thereafter Once this security feature is armed erase and program operations are disabled for EEDIVHNVR and EEDIVLNVR Modifications to the EEDIVH and EEDIVL registers are also disabled Ther...

Page 84: ...EEPROM Technical Data MC68HC908AB32 Rev 1 0 84 EEPROM MOTOROLA ...

Page 85: ...tion Register 2 88 6 2 Introduction This section describes the configuration registers CONFIG1 and CONFIG2 The configuration registers enable or disable these options Low voltage inhibit LVI in stop mode LVI reset LVI module power Stop mode recovery time 32 CGMXCLK cycles or 4096 CGMXCLK cycles COP timeout period 218 24 or 213 24 CGMXCLK cycles STOP instruction Computer operating properly module C...

Page 86: ...located at 001F and 003F The configuration register may be read at anytime 6 4 Configuration Register 1 LVISTOP LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear setting the LVISTOP bit enables the LVI to operate in stop mode Reset clears LVISTOP See Section 21 Low Voltage Inhibit LVI 1 LVI enabled during stop mode 0 LVI disabled during stop mode LVIRSTD LVI Reset Disable Bit LVIRSTD disab...

Page 87: ...riod Reset clears COPRS See Section 20 Computer Operating Properly COP 1 COP timeout period is 218 24 CGMXCLK cycles 0 COP timeout period is 213 24 CGMXCLK cycles STOP STOP Instruction Enable Bit STOP enables the STOP instruction 1 STOP instruction enabled 0 STOP instruction treated as illegal opcode COPD COP Disable Bit COPD disables the COP module See Section 20 Computer Operating Properly COP 1...

Page 88: ...M timebase divider Extra care should be exercised when using this emulation part for development of code to be run in ROM AB AS or AZ parts that the options selected by setting the CONFIG2 register match exactly the options selected on any ROM code request submitted The enable disable logic is not necessarily identical in all parts of the AB AS and AZ families If in doubt check with your local fie...

Page 89: ...er 93 7 4 5 Condition Code Register 93 7 5 Arithmetic Logic Unit ALU 96 7 6 Low Power Modes 96 7 6 1 Wait Mode 96 7 6 2 Stop Mode 97 7 7 CPU During Break Interrupts 97 7 8 Instruction Set Summary 97 7 9 Opcode Map 97 7 2 Introduction The M68HC08 CPU central processor unit is an enhanced and fully object code compatible version of the M68HC05 CPU The CPU08 Reference Manual Motorola document order n...

Page 90: ...z CPU internal bus frequency 64K byte program data memory space 16 addressing modes Memory to memory data moves without using accumulator Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions Enhanced binary coded decimal BCD data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64K bytes Low power stop and wait modes 7 4...

Page 91: ...CPU uses the accumulator to hold operands and the results of arithmetic logic operations ACCUMULATOR A INDEX REGISTER H X STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR CARRY BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG V 1 1 H I N Z C H X 0 0 0 0 7 15 15 15 7 0 Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset Unaffected by reset Figure...

Page 92: ...r is a 16 bit register that contains the address of the next location on the stack During a reset the stack pointer is preset to 00FF The reset stack pointer RSP instruction sets the least significant byte to FF and does not affect the most significant byte The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack In the stack pointer 8 bit offse...

Page 93: ...instruction or operand is fetched Jump branch and interrupt operations load the program counter with an address other than that of the next sequential location During reset the program counter is loaded with the reset vector address located at FFFE and FFFF The vector address is the address of the first instruction to be executed after exiting the reset state 7 4 5 Condition Code Register The 8 bi...

Page 94: ...lag 1 Overflow 0 No overflow H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor 1 Carry between ...

Page 95: ...service routine modifies H then the user must stack and unstack H using the PSHH and PULH instructions After the I bit is cleared the highest priority interrupt request is serviced first A return from interrupt RTI instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack After any reset the interrupt mask is set and can be cleared only by the clear interrup...

Page 96: ...ithmetic Logic Unit ALU The ALU performs the arithmetic and logic operations defined by the instruction set Refer to the CPU08 Reference Manual Motorola document order number CPU08RM AD for a description of the instructions and addressing modes and more detail about the architecture of the CPU 7 6 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 7 6...

Page 97: ...ion delay 7 7 CPU During Break Interrupts If a break module is present on the MCU the CPU starts a break interrupt by Loading the instruction register with the SWI instruction Loading the program counter with FFFC FFFD or with FEFC FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress If the break address register match occurs on the last cycle of a CP...

Page 98: ...S opr Add Immediate Value Signed to SP SP SP 16 M IMM A7 ii 2 AIX opr Add ImmediateValue Signed to H X H X H X 16 M IMM AF ii 2 AND opr AND opr AND opr AND opr X AND opr X AND X AND opr SP AND opr SP Logical AND A A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ASL opr ASLA ASLX ASL opr X ASL X ASL opr SP Arithmetic Shift Left Same as ...

Page 99: ...IRQ 0 REL 2E rr 3 BIT opr BIT opr BIT opr BIT opr X BIT opr X BIT X BIT opr SP BIT opr SP Bit Test A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A5 B5 C5 D5 E5 F5 9EE5 9ED5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 BLE opr Branch if Less Than or Equal To Signed Operands PC PC 2 rel Z N V 1 REL 93 rr 3 BLO rel Branch if Lower Same as BCS PC PC 2 rel C 1 REL 25 rr 3 BLS rel Branch if Lower or Same PC PC ...

Page 100: ...4 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BSR rel Branch to Subroutine PC PC 2 push PCL SP SP 1 push PCH SP SP 1 PC PC rel REL AD rr 4 CBEQ opr rel CBEQA opr rel CBEQX opr rel CBEQ opr X rel CBEQ X rel CBEQ opr SP rel Compare and Branch if Equal PC PC 3 rel A M 00 PC PC 3 rel A M 00 PC PC 3 rel X M 00 PC PC 3 rel A M 00 PC PC 2 rel A M 00 PC PC 4 rel A M 00 DIR IMM IMM IX1 IX SP1 31...

Page 101: ...CPX opr SP Compare X with M X M IMM DIR EXT IX2 IX1 IX SP1 SP2 A3 B3 C3 D3 E3 F3 9EE3 9ED3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 DAA Decimal Adjust A A 10 U INH 72 2 DBNZ opr rel DBNZA rel DBNZX rel DBNZ opr X rel DBNZ X rel DBNZ opr SP rel Decrement and Branch if Not Zero A A 1 or M M 1 or X X 1 PC PC 3 rel result 0 PC PC 2 rel result 0 PC PC 2 rel result 0 PC PC 3 rel result 0 PC PC 2 re...

Page 102: ...sh PCL SP SP 1 Push PCH SP SP 1 PC Unconditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 LDA opr LDA opr LDA opr LDA opr X LDA opr X LDA X LDA opr SP LDA opr SP Load A from M A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 LDHX opr LDHX opr Load H X from M H X M M 1 0 IMM DIR 45 55 ii jj dd 3 4 LDX opr LDX...

Page 103: ...one INH 9D 1 NSA Nibble Swap A A A 3 0 A 7 4 INH 62 3 ORA opr ORA opr ORA opr ORA opr X ORA opr X ORA X ORA opr SP ORA opr SP Inclusive OR A and M A A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 AA BA CA DA EA FA 9EEA 9EDA ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 PSHA Push A onto Stack Push A SP SP 1 INH 87 2 PSHH Push H onto Stack Push H SP SP 1 INH 8B 2 PSHX Push X onto Stack Push X SP SP 1 INH 89 2...

Page 104: ... IX2 IX1 IX SP1 SP2 A2 B2 C2 D2 E2 F2 9EE2 9ED2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 SEC Set Carry Bit C 1 1 INH 99 1 SEI Set Interrupt Mask I 1 1 INH 9B 2 STA opr STA opr STA opr X STA opr X STA X STA opr SP STA opr SP Store A in M M A 0 DIR EXT IX2 IX1 IX SP1 SP2 B7 C7 D7 E7 F7 9EE7 9ED7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 STHX opr Store H X in M M M 1 H X 0 DIR 35 dd 4 STOP Enable...

Page 105: ... CCR SP SP 1 I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte 1 INH 83 9 TAP Transfer A to CCR CCR A INH 84 2 TAX Transfer A to X X A INH 97 1 TPA Transfer CCR to A A CCR INH 85 1 TST opr TSTA TSTX TST opr X TST X TST opr SP Test for Negative or Zero A 00 or X 00 or M 00 0 DIR INH INH IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 3 1 1 3 2 4 TSX Transfer SP to H X H X SP 1 INH 95 2 TXA T...

Page 106: ...byte in indexed 8 bit offset addressing SP Stack pointer H Half carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte Logical AND IMD Immediate source to direct destination addressing mode Logical OR IMM Immediate addressing mode Logical EXCLU...

Page 107: ... 5 BRSET4 3 DIR 4 BSET4 2 DIR 3 BHCC 2 REL 4 LSL 2 DIR 1 LSLA 1 INH 1 LSLX 1 INH 4 LSL 2 IX1 5 LSL 3 SP1 3 LSL 1 IX 2 PULX 1 INH 1 CLC 1 INH 2 EOR 2 IMM 3 EOR 2 DIR 4 EOR 3 EXT 4 EOR 3 IX2 5 EOR 4 SP2 3 EOR 2 IX1 4 EOR 3 SP1 2 EOR 1 IX 9 5 BRCLR4 3 DIR 4 BCLR4 2 DIR 3 BHCS 2 REL 4 ROL 2 DIR 1 ROLA 1 INH 1 ROLX 1 INH 4 ROL 2 IX1 5 ROL 3 SP1 3 ROL 1 IX 2 PSHX 1 INH 1 SEC 1 INH 2 ADC 2 IMM 3 ADC 2 DI...

Page 108: ...Central Processor Unit CPU Technical Data MC68HC908AB32 Rev 1 0 108 Central Processor Unit CPU MOTOROLA ...

Page 109: ...s from Internal Sources 114 8 4 2 1 Power On Reset 115 8 4 2 2 Computer Operating Properly COP Reset 116 8 4 2 3 Illegal Opcode Reset 117 8 4 2 4 Illegal Address Reset 117 8 4 2 5 Low Voltage Inhibit LVI Reset 117 8 5 SIM Counter 117 8 5 1 SIM Counter during Power On Reset 118 8 5 2 SIM Counter during Stop Mode Recovery 118 8 5 3 SIM Counter and Reset States 118 8 6 Exception Control 118 8 6 1 Int...

Page 110: ...ities A block diagram of the SIM is shown in Figure 8 1 Figure 8 2 is a summary of the SIM I O registers The SIM is a system state controller that coordinates CPU and exception timing The SIM is responsible for Bus clock generation and control for CPU and peripherals Stop wait reset break entry and recovery Internal clock control Master reset control including power on reset POR and COP timeout In...

Page 111: ...ess bus IDB Internal data bus PORRST Signal from the power on reset module to the SIM IRST Internal reset signal R W Read write signal STOP WAIT CLOCK CONTROL CLOCK GENERATORS POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE MODULE STOP MODULE WAIT CPU STOP FROM CPU CPU WAIT FROM CPU SIMOSCEN TO CGM CGMOUT FROM CGM INTERNAL CLOCKS MASTER RESET CONTROL R...

Page 112: ...9 Clock Generator Module CGM Figure 8 3 CGM Clock Signals Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 FE00 SIM Break Status Register SBSR Read R R R R R R SBSW R Write Note Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears SBSW FE01 SIM Reset Status Register SRSR Read POR PIN COP ILOP ILAD 0 LVI 0 Write POR 1 0 0 0 0 0 0 0 FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write R...

Page 113: ...g this entire period The IBUS clocks start upon completion of the timeout 8 3 3 Clocks in Stop and Wait Modes Upon exit from stop mode by an interrupt break or reset the SIM allows CGMXCLK to clock the SIM counter The CPU and peripheral clocks do not become active until after the stop delay timeout This timeout is selectable as 4096 or 32 CGMXCLK cycles See 8 7 2 Stop Mode In wait mode the CPU clo...

Page 114: ... CGMXCLK cycles assuming that neither the POR nor the LVI was the source of the reset See Table 8 2 for details Figure 8 4 shows the relative timing Figure 8 4 External Reset Timing 8 4 2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow for resetting of external peripherals The internal reset signal IRST continues to be ass...

Page 115: ...set module POR generates a pulse to indicate that power on has occurred The external reset pin RST is held low while the SIM counter counts out 4096 CGMXCLK cycles 64 CGMXCLK cycles later the CPU and memories are released from reset to allow the reset vector sequence to occur At power on the following events occur A POR pulse is generated The internal reset signal is asserted The SIM enables CGMOU...

Page 116: ...meout a value any value should be written to location FFFF Writing to location FFFF clears the COP counter and bits 12 through 4 of the SIM counter The SIM counter output which occurs at least every 213 24 CGMXCLK cycles drives the COP counter The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout The COP module is disabled if t...

Page 117: ...ch from an unmapped address does not generate a reset The SIM actively pulls down the RST pin for all internal reset sources 8 4 2 5 Low Voltage Inhibit LVI Reset The low voltage inhibit module LVI asserts its output to the SIM when the VDD voltage falls to the trip voltage VLVII The LVI bit in the SIM reset status register SRSR is set and the external reset pin RST is held low while the SIM count...

Page 118: ...er 1 CONFIG1 If the SSREC bit is a logic 1 then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles This is ideal for applications using canned oscillators that do not require long start up times from stop mode External crystal applications should use the full stop recovery time that is with SSREC cleared 8 5 3 SIM Counter and Reset States External r...

Page 119: ...overy timing Figure 8 8 Interrupt Entry Timing Figure 8 9 Interrupt Recovery Timing Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing The arbitration result is a constant that the CPU uses to determine which vector to fetch Once an interrupt is latched by the SIM no other interrupt may take precedence regardless of priority until the latched interr...

Page 120: ...re interrupts If interrupts are not masked I bit clear in the condition code register and if the corresponding interrupt enable bit is set the SIM proceeds with interrupt processing otherwise the next instruction is fetched and executed NO NO NO YES NO NO YES YES AS MANY INTERRUPTS I BIT SET FROM RESET BREAK I BIT SET IRQ INTERRUPT SWI INSTRUCTION RTI INSTRUCTION FETCH NEXT INSTRUCTION UNSTACK CPU...

Page 121: ...ver in the case of the INT1 RTI prefetch this is a redundant operation NOTE To maintain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode software should save the H register and then restore it prior to exiting the routine 8 6 1 2 SWI Instruction The SWI i...

Page 122: ...or High FFE3 SPI Transmit Vector Low FFE4 SPI Receive Vector High FFE5 SPI Receive Vector Low FFE6 Timer B Overflow Vector High FFE7 Timer B Overflow Vector Low FFE8 Timer B Channel 1 Vector High FFE9 Timer B Channel 1 Vector Low FFEA Timer B Channel 0 Vector High FFEB Timer B Channel 0 Vector Low FFEC Timer A Overflow Vector High FFED Timer A Overflow Vector Low FFEE Timer A Channel 3 Vector High...

Page 123: ...s contained in other modules can be cleared during break mode The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit BCFE in the SIM break flag control register SBFCR Protecting flags in break mode ensures that set flags will not be cleared while in break mode This protection allows registers to be freely read and written during ...

Page 124: ...Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred In wait mode the CPU clocks are inactive Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode wait mode can also be exited by a reset or break A break interrupt during wait mode sets t...

Page 125: ... SIM disables the clock generator module outputs CGMOUT and CGMXCLK in stop mode stopping the CPU and peripherals Stop recovery time is selectable using the SSREC bit in the configuration register 1 CONFIG1 If SSREC is set stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 This is ideal for applications using canned oscillators that do not require long start up times ...

Page 126: ... instruction until the beginning of stop recovery It is then used to time the recovery period Figure 8 15 shows stop mode entry timing Figure 8 15 Stop Mode Entry Timing Figure 8 16 Stop Mode Recovery from Interrupt or Break STOP ADDR 1 SAME SAME IAB IDB PREVIOUS DATA NEXT OPCODE SAME STOP ADDR SAME R W CPUSTOP NOTE Previous data can be operand data or the STOP opcode depending on the last instruc...

Page 127: ... wait mode after exiting from a break interrupt SBSW can be cleared by writing a logic 0 to it Reset clears SBSW 1 Stop or wait mode was exited by break interrupt 0 Stop or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine The user can modify the return address on the stack by subtracting one from it The following code is an example of this Table 8 4 S...

Page 128: ...orks if the H register has been pushed onto the stack in the break service routine software This code should be executed at the end of the break service routine software HIBYTE EQU 5 LOBYTE EQU 6 If not SBSW do RTI BRCLR SBSW SBSR RETURN See if STOP or WAIT mode was exited by break TST LOBYTE SP If RETURNLO is not 0 BNE DOLO then just decrement low byte DEC HIBYTE SP Else deal with high byte too D...

Page 129: ...s 0 POR or read of SRSR LVI Low Voltage Inhibit Reset Bit 1 Last reset was caused by the LVI circuit 0 POR or read of SRSR 8 8 3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status regis...

Page 130: ...System Integration Module SIM Technical Data MC68HC908AB32 Rev 1 0 130 System Integration Module SIM MOTOROLA ...

Page 131: ... 4 2 5 Special Programming Exceptions 139 9 4 3 Base Clock Selector Circuit 140 9 4 4 CGM External Connections 140 9 5 I O Signals 142 9 5 1 Crystal Amplifier Input Pin OSC1 142 9 5 2 Crystal Amplifier Output Pin OSC2 142 9 5 3 External Filter Capacitor Pin CGMXFC 142 9 5 4 PLL Analog Power Pin VDDA 142 9 5 5 Oscillator Enable Signal SIMOSCEN 142 9 5 6 Crystal Output Frequency Signal CGMXCLK 143 9...

Page 132: ...o generates the base clock signal CGMOUT from which the system integration module SIM derives the system clocks CGMOUT is based on either the crystal clock divided by two or the phase locked loop PLL clock CGMVCLK divided by two The PLL is a frequency generator designed for use with 1MHz to 8MHz crystals or ceramic resonators The PLL can generate an 8MHz bus frequency without using a higher freque...

Page 133: ...trolled circuit selects either CGMXCLK divided by two or the VCO clock CGMVCLK divided by two as the base clock CGMOUT The SIM derives the system clocks from CGMOUT Figure 9 1 shows the structure of the CGM Figure 9 1 CGM Block Diagram BCS PHASE DETECTOR LOOP FILTER FREQUENCY DIVIDER VOLTAGE CONTROLLED OSCILLATOR BANDWIDTH CONTROL LOCK DETECTOR CLOCK CGMXCLK CGMOUT CGMVDV CGMVCLK SIMOSCEN CRYSTAL ...

Page 134: ... used by other modules which require precise timing for operation The duty cycle of CGMXCLK is not guaranteed to be 50 and depends on external factors including the crystal and related external components An externally generated clock can also feed the OSC1 pin of the crystal oscillator circuit For this configuration the external clock should be connected to the OSC1 pin and the OSC2 pin allowed t...

Page 135: ...alf to twice the center of range frequency fVRS Modulating the voltage on the CGMXFC pin changes the frequency within this range By design fVRS is equal to the nominal center of range frequency fNOM 4 9152MHz times a linear factor L or L fNOM CGMRCLK is the PLL reference clock a buffered version of CGMXCLK CGMRCLK runs at a frequency fRCLK and is fed to the PLL through a buffer The buffer output i...

Page 136: ...ter is manually or automatically configurable into one of two operating modes Acquisition mode in acquisition mode the filter can make large frequency corrections to the VCO This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the resulting VCO frequency is much different from the desired frequency When in acquisition mode the ACQ bit is clear in the PLL bandwidth ...

Page 137: ...e appropriate action depending on the application See 9 7 Interrupts for information and precautions on using interrupts The following conditions apply when the PLL is in automatic bandwidth control mode The ACQ bit see 9 6 2 PLL Bandwidth Control Register PBWC is a read only indicator of the mode of the filter See 9 4 2 2 Acquisition and Tracking Modes The ACQ bit is set when the VCO frequency is...

Page 138: ...n the PLL control register PCTL Software must wait a given time tAL after entering tracking mode before selecting the PLL as the clock source to CGMOUT BCS 1 The LOCK bit is disabled CPU interrupts from the CGM are disabled 9 4 2 4 Programming the PLL The following procedure shows how to program the PLL NOTE The round function in the following equations means that the real number should be rounded...

Page 139: ...ion s tolerance of fVCLKDES and fVRS must be as close as possible to fVCLK NOTE Exceeding the recommended maximum bus frequency or VCO frequency can cause the MCU to crash 9 Program the PLL registers accordingly a In the upper 4 bits of the PLL programming register PPG program the binary equivalent of N b In the lower 4 bits of the PLL programming register PPG program the binary equivalent of L 9 ...

Page 140: ...e selected clock CGMXCLK or CGMVCLK The BCS bit in the PLL control register PCTL selects which clock drives CGMOUT The VCO clock cannot be selected as the base clock source if the PLL is not turned on The PLL cannot be turned off if the VCO clock is selected The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock The VCO clock also cannot be selected as...

Page 141: ...gh frequency crystals Refer to the crystal manufacturer s data for more information Figure 9 3 also shows the external components for the PLL Bypass capacitor CBYP Filter capacitor CF Care should be taken with routing in order to minimize signal cross talk and noise See 9 10 Acquisition Lock Time Specifications for routing information and more information on the filter capacitor s value and its ef...

Page 142: ... filter out phase corrections A small external capacitor is connected to this pin NOTE To prevent noise problems CF should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the CF connection 9 5 4 PLL Analog Power Pin VDDA VDDA is a power pin used by the analog portions of the PLL The pin should be connected to the same voltage p...

Page 143: ...stable at start up 9 5 7 CGM Base Clock Output CGMOUT CGMOUT is the clock output of the CGM This signal goes to the SIM which generates the MCU clocks CGMOUT is a 50 duty cycle clock running at twice the bus frequency CGMOUT is software programmable to be either the oscillator output CGMXCLK divided by two or the VCO clock CGMVCLK divided by two 9 5 8 CGM CPU Interrupt CGMINT CGMINT is the interru...

Page 144: ... 0 Write Reset 0 0 0 0 0 0 0 0 001E PLL Programming Register PPG Read MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 Write Reset 0 1 1 0 0 1 1 0 Unimplemented NOTES 1 When AUTO 0 PLLIE is forced to logic zero and is read only 2 When AUTO 0 PLLF and LOCK read as logic zero 3 When AUTO 1 ACQ is read only 4 When PLLON 0 or VRS 7 4 0 BCS is forced to logic zero and is read only 5 When PLLON 1 the PLL program...

Page 145: ...L control register Reset clears the PLLF bit 1 Change in lock condition 0 No change in lock condition NOTE The PLLF bit should not be inadvertently cleared Any read or read modify write operation on the PLL control register clears the PLLF bit PLLON PLL On Bit This read write bit activates the PLL and enables the VCO clock CGMVCLK PLLON cannot be cleared if the VCO clock is driving the base clock ...

Page 146: ...when PLLON is clear If the PLL is off PLLON 0 selecting CGMVCLK requires two writes to the PLL control register See 9 4 3 Base Clock Selector Circuit Bits 3 0 Unimplemented bits These bits provide no function and always read as 1 9 6 2 PLL Bandwidth Control Register PBWC The PLL bandwidth control register does the following Selects automatic or manual software controlled bandwidth control mode Ind...

Page 147: ...ect or unlocked ACQ Acquisition Mode Bit When the AUTO bit is set ACQ is a read only bit that indicates whether the PLL is in acquisition mode or tracking mode When the AUTO bit is clear ACQ is a read write bit that controls whether the PLL is in acquisition or tracking mode In automatic bandwidth control mode AUTO 1 the last written value from manual operation is stored in a temporary location an...

Page 148: ...gister PPG The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO MUL 7 4 Multiplier Select Bits These read write bits control the modulo feedback divider that selects the VCO frequency multiplier N See 9 4 2 1 PLL Circuits and 9 4 2 4 Programming the PLL A value of 0 in the multipl...

Page 149: ...ogramming Exceptions A value of 0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL See 9 4 3 Base Clock Selector Circuit and 9 4 2 5 Special Programming Exceptions for more information Reset initializes the bits to 6 to give a default range multiply value of 6 NOTE The VCO range select bits have built in protection that prevents them from being written when the PLL ...

Page 150: ... the PCTL When the PLL exits lock the VCO clock frequency is corrupt and appropriate precautions should be taken If the application is not frequency sensitive interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations NOTE Software can select CGMVCLK 2 as the CGMOUT source even if the PLL is not locked LOCK 0 There...

Page 151: ...IM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See Section 8 System Integration Module SIM To allow software to clear status bits during a break interrupt a 1 should be written to the BCFE bit If a status bit is cleared during the break stat...

Page 152: ...kHz 5kHz 5 of the 100kHz step input Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances Therefore the acquisition or lock time varies according to the original error in the output Minor errors may not even be registered Typical PLL applications prefer to use this definitio...

Page 153: ...d indirectly affect the acquisition time The most critical parameter which affects the reaction times of the PLL is the reference frequency fRDV This frequency is the input to the phase detector and controls how often the PLL makes corrections For stability the corrections must be small compared to the desired frequency so several corrections are required to reduce the frequency error Therefore th...

Page 154: ...it board and even humidity or circuit board contamination 9 10 3 Choosing a Filter Capacitor As described in 9 10 2 Parametric Influences On Reaction Time the external filter capacitor CF is critical to the stability and reaction time of the PLL The PLL is also dependent on reference frequency and supply voltage The value of the capacitor must therefore be chosen with supply potential and referenc...

Page 155: ... PLL parameters KACQ is the K factor when the PLL is configured in acquisition mode and KTRK is the K factor when the PLL is configured in tracking mode See 9 4 2 2 Acquisition and Tracking Modes Note the inverse proportionality between the lock time and the reference frequency In automatic bandwidth control mode the acquisition and lock times are quantized into units based on the reference freque...

Page 156: ...tAL is an integer multiple of nTRK fRDV Also since the average frequency over the entire measurement period must be within the specified tolerance the total time usually is longer than tLOCK as calculated above In manual mode it is usually necessary to wait considerably longer than tLOCK before selecting the PLL clock see 9 4 3 Base Clock Selector Circuit because the factors described in 9 10 2 Pa...

Page 157: ... 4 Functional Description 158 10 4 1 Entering Monitor Mode 160 10 4 2 Data Format 161 10 4 3 Echoing 162 10 4 4 Break Signal 162 10 4 5 Commands 163 10 4 6 Baud Rate 166 10 5 Security 167 10 6 Extended Security 168 10 2 Introduction This section describes the monitor ROM MON The monitor ROM allows complete testing of the MCU through a single wire interface with a host computer ...

Page 158: ...omputer via a standard RS 232 interface While simple monitor commands can access any memory address the MCU has a FLASH security feature to prevent external viewing of the contents of FLASH Proper procedures must be followed to verify FLASH content Access to the FLASH is denied to unauthorized users of customer specified software In monitor mode the MCU can execute host computer code in RAM while ...

Page 159: ...7 MC74HC125 RST IRQ OSC1 OSC2 VSS VDD PTA0 VDD 10 kΩ 0 1 µF 10 Ω 6 5 2 4 3 1 DB 25 2 3 7 20 18 17 19 16 15 VDD VDD VDD 20 pF 20 pF 10 µF 10 µF 10 µF 10 µF 1 2 4 7 14 3 0 1 µF 4 9152 MHz 10 kΩ PTC3 VDD 10 kΩ B A NOTES Position B Bus clock CGMXCLK 2 See NOTES 5 6 PTC0 PTC1 VDD 10 kΩ Position A Bus clock CGMXCLK 4 or CGMVCLK 4 VCGMXFC 0 1 µF VDDA VDDA MC68HC908AB32 ...

Page 160: ...code execution from the internal monitor firmware instead of user code The COP module is disabled in monitor mode as long as VTST see Section 23 Electrical Specifications is applied to either the IRQ pin or the RST pin See Section 8 System Integration Module SIM for more information on modes of operation NOTE Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide by two st...

Page 161: ...le 10 2 Mode Differences Modes Functions COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled FFFE FFFF FFFC FFFD FFFC FFFD Monitor Disabled 1 Notes 1 If the high voltage VTST is removed from the IRQ pin while in monitor mode the SIM asserts its COP enable output The COP can be enabled or disabled by the COPD bit in the configuration...

Page 162: ...last byte of the command Figure 10 4 Read Transaction 10 4 4 Break Signal A start bit followed by nine low bits is a break signal See Figure 10 5 When the monitor receives a break signal it drives the PTA0 pin high for the duration of two bits before echoing the break signal Figure 10 5 Break Transaction ADDR HIGH READ READ ADDR HIGH ADDR LOW ADDR LOW DATA ECHO SENT TO MONITOR RESULT 0 1 2 3 4 5 6...

Page 163: ...ck pointer RUN run user program A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64k byte memory map Table 10 3 READ Read Memory Command Description Read byte from memory Operand Specifies 2 byte address in high byte low byte order Data Returned Returns contents of specified address Opcode 4A Command Sequence READ READ ECHO SENT TO MONITOR ADDRESS HIGH...

Page 164: ... byte Data Returned None Opcode 49 Command Sequence Table 10 5 IREAD Indexed Read Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2 byte address in high byte low byte order Data Returned Returns contents of next two addresses Opcode 1A Command Sequence WRITE WRITE ECHO SENT TO MONITOR ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA IREAD IRE...

Page 165: ...ss accessed 1 Operand Specifies single data byte Data Returned None Opcode 19 Command Sequence Table 10 7 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte low byte order Opcode 0C Command Sequence IWRITE IWRITE ECHO SENT TO MONITOR DATA DATA READSP READSP ECHO SENT TO MONITOR SP RETURN SP HIGH LOW ...

Page 166: ...utput CGMOUT is driven by the PLL the baud rate is determined by the MUL 7 4 bits in the PLL programming register PPG See Section 9 Clock Generator Module CGM Table 10 8 RUN Run User Program Command Description Executes RTI instruction Operand None Data Returned None Opcode 28 Command Sequence RUN RUN ECHO SENT TO MONITOR Table 10 9 Monitor Baud Rate Selection Monitor Baud Rate VCO Frequency Multi...

Page 167: ...MCU waits after the power on reset for the host to send the eight security bytes on pin PTA0 If the received bytes match those at locations FFF6 FFFD the host bypasses the security feature and can read all FLASH locations and execute code from FLASH Security remains bypassed until a power on reset occurs If the reset was not a power on reset security remains bypassed and security code entry is not...

Page 168: ...e MCU remains in monitor mode but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset The MCU monitor commands are still valid and user software can execute from RAM A bulk erase operation is possible erasing the entire FLASH memory including the security bytes at FFF6 FFFD 10 6 Extended Security To further disable monitor mode fu...

Page 169: ...ut Compare 176 11 5 4 Pulse Width Modulation PWM 177 11 5 4 1 Unbuffered PWM Signal Generation 178 11 5 4 2 Buffered PWM Signal Generation 179 11 5 4 3 PWM Initialization 180 11 6 Interrupts 181 11 7 Low Power Modes 181 11 7 1 Wait Mode 182 11 7 2 Stop Mode 182 11 8 TIMA During Break Interrupts 182 11 9 I O Signals 183 11 9 1 TIMA Clock Pin 183 11 9 2 TIMA Channel I O Pins 183 11 10 I O Registers ...

Page 170: ...A 11 3 Features Features of the TIMA include the following Four input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIMA clock input Seven frequency internal bus clock prescaler selection External TIMA clock input 4MHz maximum freq...

Page 171: ...put capture and output compare functions The TIMA counter modulo registers TAMODH TAMODL control the modulo value of the TIMA counter Software can read the TIMA counter value at any time without affecting the counting sequence The four TIMA channels are programmable independently as input capture or output compare channels 11 5 1 TIMA Counter Prescaler The TIMA clock source can be one of the seven...

Page 172: ...MPARATOR 16 BIT LATCH TACH2H TACH2L 16 BIT COMPARATOR 16 BIT LATCH TACH3H TACH3L CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 TAMODH TAMODL TRST TSTOP TOV0 CH0IE CH0F ELS1B ELS1A TOV1 CH1IE CH1MAX CH1F ELS2B ELS2A TOV2 CH2IE CH2MAX CH2F ELS3B ELS3A TOV3 CH3IE CH3MAX CH3F CH0MAX MS0B MS2B 16 BIT COUNTER INTERNAL BUS INTERNAL MS1A MS2A MS3A PTD6 TACLK PTE2 TACH0 PTE3 TACH1 PTF0 TACH2 PTF1 TACH3 INTERRUPT...

Page 173: ... 1 1 1 1 1 1 0025 Timer A Counter Modulo Register Low TAMODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0026 Timer A Channel 0 Status and Control Register TASC0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 0027 Timer A Channel 0 Register High TACH0H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 0028 Timer A Channel 0 Regis...

Page 174: ...hannel 2 Status and Control Register TASC2 Read CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX Write 0 Reset 0 0 0 0 0 0 0 0 002D Timer A Channel 2 Register High TACH2H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 002E Timer A Channel 2 Register Low TACH2L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 002F Timer A Channel 3 Status and Control Register...

Page 175: ...ew value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period Also using a TIMA overflow interrupt routine to write a new smaller output compare value may cause the compare to be missed The TIMA may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the outpu...

Page 176: ...annel 1 pin PTE3 TACH1 is available as a general purpose I O pin Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF0 TACH2 pin The TIMA channel registers of the linked pair alternately control the output Setting the MS2B bit in TIMA channel 2 status and control register TASC2 links channel 2 and channel 3 The output compare value in the TIMA ch...

Page 177: ...ear the channel pin on output compare if the state of the PWM pulse is logic one Program the TIMA to set the pin if the state of the PWM pulse is logic zero Figure 11 3PWM Period and Pulse Width The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8 bit PWM signal is variable in 256 increments Writing 00FF 2...

Page 178: ...s to synchronize unbuffered changes in the PWM pulse width on channel x When changing to a shorter pulse width enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current pulse The interrupt routine has until the end of the PWM period to write the new value When changing to a longer pulse w...

Page 179: ...0B bit is set the channel 1 pin PTE3 TACH1 is available as a general purpose I O pin Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF0 TACH2 pin The TIMA channel registers of the linked pair alternately control the pulse width of the output Setting the MS2B bit in TIMA channel 2 status and control register TASC2 links channel 2 and channel 3 The TIMA ch...

Page 180: ...te 1 to the toggle on overflow bit TOVx b Write 1 0 to clear output on compare or 1 1 to set output on compare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 11 3 NOTE In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 0 du...

Page 181: ...TOVx bit generates a 100 duty cycle output See 11 10 4 TIMA Channel Status and Control Registers 11 6 Interrupts The following TIMA sources can generate interrupt requests TIMA overflow flag TOF The TOF bit is set when the TIMA counter value rolls over to 0000 after matching the value in the TIMA counter modulo registers The TIMA overflow interrupt enable bit TOIE enables TIMA overflow CPU interru...

Page 182: ...s the TIMA counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 8 8 3 SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic one to the BCFE bit If a...

Page 183: ...ck Select the PTD6 TACLK input by writing logic 1s to the three prescaler select bits PS 2 0 See 11 10 1 TIMA Status and Control Register The minimum TACLK pulse width TACLKLMIN or TACLKHMIN is The maximum TACLK frequency is bus frequency 2 PTD6 TACLK is available as a general purpose I O pin when not used as the TIMA clock input When the PTD6 TACLK pin is the TIMA clock input it is an input regar...

Page 184: ...us and control registers TASC0 TASC1 TASC2 and TASC3 TIMA channel registers TACH0H TACH0L TACH1H TACH1L TACH2H TACH2L and TACH3H TACH3L 11 10 1 TIMA Status and Control Register The TIMA status and control register does the following Enables TIMA overflow interrupts Flags TIMA overflows Stops the TIMA counter Resets the TIMA counter Prescales the TIMA counter clock Address 0020 Bit 7 6 5 4 3 2 1 Bi...

Page 185: ...erflow Interrupt Enable Bit This read write bit enables TIMA overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIMA overflow interrupts enabled 0 TIMA overflow interrupts disabled TSTOP TIMA Stop Bit This read write bit stops the TIMA counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIMA counter until software clears the TSTOP bit 1 TI...

Page 186: ...ct the latched TACNTL value until TACNTL is read Reset clears the TIMA counter registers Setting the TIMA reset bit TRST also clears the TIMA counter registers NOTE If you read TACNTH during a break interrupt be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt Otherwise TACNTL retains the value latched during the break Table 11 2 Prescaler Selection PS2 PS1 PS0 TIM Clock...

Page 187: ... bit and overflow interrupts until the low byte TAMODL is written Reset sets the TIMA counter modulo registers NOTE Reset the TIMA counter before writing to the TIMA counter modulo registers Address 0023 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 6 TIMA Counter Register Low TACNTL Address 0024 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 1...

Page 188: ...or toggling output on output compare Selects rising edge falling edge or any edge as the active input capture trigger Selects output toggling on TIMA overflow Selects 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation Address 0026 Bit 7 6 5 4 3 2 1 Bit 0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 11 9 TIMA Channel 0 Status and...

Page 189: ...te then writing logic zero to CHxF has no effect Therefore an interrupt request cannot be lost due to inadvertent clearing of CHxF Reset clears the CHxF bit Writing a logic one to CHxF has no effect 1 Input capture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIMA CPU interrupts on channel x Reset ...

Page 190: ...put compare PWM operation See Table 11 3 1 Unbuffered output compare PWM operation 0 Input capture operation When ELSxB A 00 this read write bit selects the initial output level of the TBCHx pin See Table 11 3 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit set the TSTOP and TRST bits in the...

Page 191: ...he same time CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic zero setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As Figure 11 13 shows the CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared Table 11 3 Mode Edge and Level Selection MSxB ...

Page 192: ...gisters TACHxH inhibits input captures until the low byte TACHxL is read In output compare mode MSxB MSxA 0 0 writing to the high byte of the TIMA channel x registers TACHxH inhibits output compares until the low byte TACHxL is written OUTPUT OVERFLOW TACHx PERIOD CHxMAX OVERFLOW OVERFLOW OVERFLOW OVERFLOW COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Address 0027 Bit 7 6 5 4 3 2 1 Bit 0 Re...

Page 193: ...igh TACH1H Address 002B Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 11 17 TIMA Channel 1 Register Low TACH1L Address 002D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 11 18 TIMA Channel 2 Register High TACH2H Address 002E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset ...

Page 194: ... Address 0030 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 11 20 TIMA Channel 3 Register High TACH3H Address 0031 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 11 21 TIMA Channel 3 Register Low TACH3L ...

Page 195: ...ut Compare 202 12 5 4 Pulse Width Modulation PWM 203 12 5 4 1 Unbuffered PWM Signal Generation 204 12 5 4 2 Buffered PWM Signal Generation 205 12 5 4 3 PWM Initialization 206 12 6 Interrupts 207 12 7 Low Power Modes 207 12 7 1 Wait Mode 208 12 7 2 Stop Mode 208 12 8 TIMB During Break Interrupts 208 12 9 I O Signals 209 12 9 1 TIMB Clock Pin 209 12 9 2 TIMB Channel I O Pins 209 12 10 I O Registers ...

Page 196: ...B 12 3 Features Features of the TIMB include the following Four input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIMB clock input Seven frequency internal bus clock prescaler selection External TIMB clock input 4MHz maximum freq...

Page 197: ...ut capture and output compare functions The TIMB counter modulo registers TBMODH TBMODL control the modulo value of the TIMB counter Software can read the TIMB counter value at any time without affecting the counting sequence The four TIMB channels are programmable independently as input capture or output compare channels 12 5 1 TIMB Counter Prescaler The TIMB clock source can be one of the seven ...

Page 198: ...MPARATOR 16 BIT LATCH TBCH2H TBCH2L 16 BIT COMPARATOR 16 BIT LATCH TBCH3H TBCH3L CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 TBMODH TBMODL TRST TSTOP TOV0 CH0IE CH0F ELS1B ELS1A TOV1 CH1IE CH1MAX CH1F ELS2B ELS2A TOV2 CH2IE CH2MAX CH2F ELS3B ELS3A TOV3 CH3IE CH3MAX CH3F CH0MAX MS0B MS2B 16 BIT COUNTER INTERNAL BUS INTERNAL MS1A MS2A MS3A PTD4 TBCLK PTF4 TBCH0 PTF5 TBCH1 PTF2 TBCH2T PTF3 TBCH3 INTERRUP...

Page 199: ... 1 1 1 1 1 1 0044 Timer B Counter Modulo Register Low TBMODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0045 Timer B Channel 0 Status and Control Register TBSC0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 0046 Timer B Channel 0 Register High TBCH0H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 0047 Timer B Channel 0 Regis...

Page 200: ...hannel 2 Status and Control Register TBSC2 Read CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX Write 0 Reset 0 0 0 0 0 0 0 0 0033 Timer B Channel 2 Register High TBCH2H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 0034 Timer B Channel 2 Register Low TBCH2L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 0035 Timer B Channel 3 Status and Control Register...

Page 201: ...ew value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period Also using a TIMB overflow interrupt routine to write a new smaller output compare value may cause the compare to be missed The TIMB may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the outpu...

Page 202: ...annel 1 pin PTF5 TBCH1 is available as a general purpose I O pin Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF2 TBCH2 pin The TIMB channel registers of the linked pair alternately control the output Setting the MS2B bit in TIMB channel 2 status and control register TBSC2 links channel 2 and channel 3 The output compare value in the TIMB ch...

Page 203: ...ear the channel pin on output compare if the state of the PWM pulse is logic one Program the TIMB to set the pin if the state of the PWM pulse is logic zero Figure 12 3PWM Period and Pulse Width The value in the TIMB counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8 bit PWM signal is variable in 256 increments Writing 00FF 2...

Page 204: ...s to synchronize unbuffered changes in the PWM pulse width on channel x When changing to a shorter pulse width enable channel x output compare interrupts and write the new value in the output compare interrupt routine The output compare interrupt occurs at the end of the current pulse The interrupt routine has until the end of the PWM period to write the new value When changing to a longer pulse w...

Page 205: ...0B bit is set the channel 1 pin PTF5 TBCH1 is available as a general purpose I O pin Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF2 TBCH2 pin The TIMB channel registers of the linked pair alternately control the pulse width of the output Setting the MS2B bit in TIMB channel 2 status and control register TBSC2 links channel 2 and channel 3 The TIMB ch...

Page 206: ...ite 1 to the toggle on overflow bit TOVx b Write 1 0 to clear output on compare or 1 1 to set output on compare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 12 3 NOTE In PWM signal generation do not program the PWM channel to toggle on output compare Toggling on output compare prevents reliable 0 d...

Page 207: ...TOVx bit generates a 100 duty cycle output See 12 10 4 TIMB Channel Status and Control Registers 12 6 Interrupts The following TIMB sources can generate interrupt requests TIMB overflow flag TOF The TOF bit is set when the TIMB counter value rolls over to 0000 after matching the value in the TIMB counter modulo registers The TIMB overflow interrupt enable bit TOIE enables TIMB overflow CPU interru...

Page 208: ...s the TIMB counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 8 8 3 SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic one to the BCFE bit If a...

Page 209: ...lect the PTD4 TBCLK input by writing logic 1s to the three prescaler select bits PS 2 0 See 12 10 1 TIMB Status and Control Register The minimum TBCLK pulse width TBCLKLMIN or TBCLKHMIN is The maximum TBCLK frequency is bus frequency 2 PTD4 TBCLK is available as a general purpose I O pin when not used as the TIMB clock input When the PTD4 TBCLK pin is the TIMB clock input it is an input regardless...

Page 210: ...us and control registers TBSC0 TBSC1 TBSC2 and TBSC3 TIMB channel registers TBCH0H TBCH0L TBCH1H TBCH1L TBCH2H TBCH2L and TBCH3H TBCH3L 12 10 1 TIMB Status and Control Register The TIMB status and control register does the following Enables TIMB overflow interrupts Flags TIMB overflows Stops the TIMB counter Resets the TIMB counter Prescales the TIMB counter clock Address 0040 Bit 7 6 5 4 3 2 1 Bi...

Page 211: ...erflow Interrupt Enable Bit This read write bit enables TIMB overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 TIMB overflow interrupts enabled 0 TIMB overflow interrupts disabled TSTOP TIMB Stop Bit This read write bit stops the TIMB counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIMB counter until software clears the TSTOP bit 1 TI...

Page 212: ...ct the latched TBCNTL value until TBCNTL is read Reset clears the TIMB counter registers Setting the TIMB reset bit TRST also clears the TIMB counter registers NOTE If you read TBCNTH during a break interrupt be sure to unlatch TBCNTL by reading TBCNTL before exiting the break interrupt Otherwise TBCNTL retains the value latched during the break Table 12 2 Prescaler Selection PS2 PS1 PS0 TIM Clock...

Page 213: ... bit and overflow interrupts until the low byte TBMODL is written Reset sets the TIMB counter modulo registers NOTE Reset the TIMB counter before writing to the TIMB counter modulo registers Address 0042 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 6 TIMB Counter Register Low TBCNTL Address 0043 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 1...

Page 214: ...or toggling output on output compare Selects rising edge falling edge or any edge as the active input capture trigger Selects output toggling on TIMB overflow Selects 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation Address 0045 Bit 7 6 5 4 3 2 1 Bit 0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 12 9 TIMB Channel 0 Status and...

Page 215: ...te then writing logic zero to CHxF has no effect Therefore an interrupt request cannot be lost due to inadvertent clearing of CHxF Reset clears the CHxF bit Writing a logic one to CHxF has no effect 1 Input capture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIMB CPU interrupts on channel x Reset ...

Page 216: ...put compare PWM operation See Table 12 3 1 Unbuffered output compare PWM operation 0 Input capture operation When ELSxB A 00 this read write bit selects the initial output level of the TBCHx pin See Table 12 3 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit set the TSTOP and TRST bits in the...

Page 217: ...he same time CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic zero setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As Figure 12 13 shows the CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared Table 12 3 Mode Edge and Level Selection MSxB ...

Page 218: ...gisters TBCHxH inhibits input captures until the low byte TBCHxL is read In output compare mode MSxB MSxA 0 0 writing to the high byte of the TIMB channel x registers TBCHxH inhibits output compares until the low byte TBCHxL is written OUTPUT OVERFLOW TBCHx PERIOD CHxMAX OVERFLOW OVERFLOW OVERFLOW OVERFLOW COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Address 0046 Bit 7 6 5 4 3 2 1 Bit 0 Re...

Page 219: ...igh TBCH1H Address 004A Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 12 17 TIMB Channel 1 Register Low TBCH1L Address 0033 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 12 18 TIMB Channel 2 Register High TBCH2H Address 0034 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset ...

Page 220: ... Address 0036 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 12 20 TIMB Channel 3 Register High TBCH3H Address 0037 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 12 21 TIMB Channel 3 Register Low TBCH3L ...

Page 221: ...Prescaler 223 13 5 Low Power Modes 224 13 5 1 Wait Mode 224 13 5 2 Stop Mode 224 13 6 PIT During Break Interrupts 224 13 7 I O Registers 225 13 7 1 PIT Status and Control Register 225 13 7 2 PIT Counter Registers 227 13 7 3 PIT Counter Modulo Registers 228 13 2 Introduction This section describes the programmable interrupt timer PIT which is a timer whose counter is clocked internally via software...

Page 222: ... the PIT The central component of the PIT is the 16 bit PIT counter that can operate as a free running counter or a modulo up counter The counter provides the timing reference for the interrupt The PIT counter modulo registers PMODH PMODL control the modulo value of the counter Software can read the counter value at any time without affecting the counting sequence Figure 13 1 PIT Block Diagram PRE...

Page 223: ... after matching the value in the PIT counter modulo registers The PIT interrupt enable bit POIE enables PIT overflow CPU interrupt requests POF and POIE are in the PIT status and control register Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 004B PIT Status and Control Register PSC Read POF POIE PSTOP 0 0 PPS2 PPS1 PPS0 Write 0 PRST Reset 0 0 1 0 0 0 0 0 004C PIT Counter Register High PCNTH Read Bit ...

Page 224: ...egister conditions or the state of the PIT counter PIT operation resumes when the MCU exits stop mode after an external interrupt 13 6 PIT During Break Interrupts A break interrupt stops the PIT counter The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to c...

Page 225: ...tus bit 13 7 I O Registers The following I O registers control and monitor operation of the PIT PIT status and control register PSC PIT counter registers PCNTH PCNTL PIT counter modulo registers PMODH PMODL 13 7 1 PIT Status and Control Register The PIT status and control register does the following Enables PIT interrupt Flags PIT overflows Stops the PIT counter Resets the PIT counter Prescales th...

Page 226: ...erflow Interrupt Enable Bit This read write bit enables PIT overflow interrupts when the POF bit becomes set Reset clears the POIE bit 1 PIT overflow interrupts enabled 0 PIT overflow interrupts disabled PSTOP PIT Stop Bit This read write bit stops the PIT counter Counting resumes when PSTOP is cleared Reset sets the PSTOP bit stopping the PIT counter until software clears the PSTOP bit 1 PIT coun...

Page 227: ...tched PCNTL value until PCNTL is read Reset clears the PIT counter registers Setting the PIT reset bit PRST also clears the PIT counter registers NOTE If you read PCNTH during a break interrupt be sure to unlatch PCNTL by reading PCNTL before exiting the break interrupt Otherwise PCNTL retains the value latched during the break Table 13 1 PIT Prescaler Selection PPS2 PPS1 PPS0 PIT Clock Source 0 0...

Page 228: ...t and overflow interrupts until the low byte PMODL is written Reset sets the PIT counter modulo registers NOTE Reset the PIT counter before writing to the PIT counter modulo registers Address 004D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 5 PIT Counter Register Low PCNTL Address 004E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9...

Page 229: ...32 14 4 3 Conversion Time 232 14 4 4 Conversion 232 14 4 5 Accuracy and Precision 233 14 5 Interrupts 233 14 6 Low Power Modes 233 14 6 1 Wait Mode 233 14 6 2 Stop Mode 233 14 7 I O Signals 233 14 7 1 ADC Analog Power Pin VDDAREF 234 14 7 2 ADC Analog Ground Pin AVSS VREFL 234 14 7 3 ADC Voltage Reference High Pin VREFH 234 14 7 4 ADC Voltage In VADIN 234 14 8 I O Registers 234 14 8 1 ADC Status a...

Page 230: ...city 8 bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 0038 ADC Status and Control Register ADSCR Read COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write Reset 0 0 0 1 1 1 1 1 0039 ADC Data Register ADR Read AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write Reset 0 0 0 0 0 0 0 0 003A ADC Cl...

Page 231: ... VADIN is converted by the successive approximation register based analog to digital converter When the conversion is completed ADC places the result in the ADC data register and sets a flag or generates an interrupt See Figure 14 2 Figure 14 2 ADC Block Diagram INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx READ PTBx PTBx DDRBx PTBx INTERRUPT LOGIC CHANNEL SELECT ADC CLOCK GENERATOR CO...

Page 232: ...he input voltage equals VREFL the ADC converts it to 00 Input voltages between VREFH and VREFL are a straight line linear conversion 14 4 3 Conversion Time Conversion starts after a write to the ADSCR One conversion will take between 16 and 17 ADC clock cycles The ADIVx and ADICLK bits should be set to provide a 1 MHz ADC clock frequency 14 4 4 Conversion In continuous conversion mode the ADC data...

Page 233: ...an put the MCU in low power consumption standby modes 14 6 1 Wait Mode The ADC continues normal operation during wait mode Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting ADCH 4 0 bits in the ADC status and control register before executing the WAIT instruction 14 6 2 Stop M...

Page 234: ...citors as close as possible to the package 14 7 2 ADC Analog Ground Pin AVSS VREFL The ADC analog portion uses AVSS VREFL as its ground pin Connect the AVSS VREFL pin to the same voltage potential as VSS NOTE Route AVSS VREFL cleanly to avoid any offset errors 14 7 3 ADC Voltage Reference High Pin VREFH VREFH is the reference voltage for the ADC 14 7 4 ADC Voltage In VADIN VADIN is the input volta...

Page 235: ...uest Reset clears the COCO bit 1 Conversion completed AIEN 0 0 Conversion not completed AIEN 0 CPU interrupt AIEN 1 AIEN ADC Interrupt Enable Bit When this bit is set an interrupt is generated at the end of an ADC conversion The interrupt signal is cleared when the data register is read or the status control register is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disa...

Page 236: ...power consumption for the MCU when the ADC is not being used NOTE Recovery from the disabled state requires one conversion cycle to stabilize The voltage levels supplied from internal reference nodes as specified in Table 14 1 are used to verify the operation of the ADC converter both in production test and for user applications Table 14 1 Mux Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Sel...

Page 237: ...ncy for the ADC ADIV 2 0 ADC Clock Prescaler Bits ADIV 2 0 form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC clock Table 14 2 shows the available clock configurations The ADC clock should be set to approximately 1 MHz Address 0039 Bit 7 6 5 4 3 2 1 Bit 0 Read AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 4 ADC Data ...

Page 238: ... to or greater than 1 MHz CGMXCLK can be used as the clock source for the ADC If CGMXCLK is less than 1 MHz use the PLL generated bus clock as the clock source As long as the internal ADC clock is at approximately 1 MHz correct operation can be guaranteed 1 Internal bus clock 0 External clock CGMXCLK Table 14 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock 1 0 0 1 A...

Page 239: ...r Transmission 247 15 5 2 3 Break Characters 248 15 5 2 4 Idle Characters 248 15 5 2 5 Inversion of Transmitted Output 249 15 5 2 6 Transmitter Interrupts 249 15 5 3 Receiver 250 15 5 3 1 Character Length 250 15 5 3 2 Character Reception 250 15 5 3 3 Data Sampling 252 15 5 3 4 Framing Errors 254 15 5 3 5 Baud Rate Tolerance 254 15 5 3 6 Receiver Wakeup 257 15 5 3 7 Receiver Interrupts 258 15 5 3 8...

Page 240: ...CI module which allows high speed asynchronous communications with peripheral devices and other MCUs NOTE References to DMA direct memory access and associated functions are only valid if the MCU has a DMA module This MCU does not have the DMA function Any DMA related register bits should be left in their reset state for normal MCU operation 15 3 Features Features of the SCI module include the fol...

Page 241: ... 241 Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight interrupt flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection ...

Page 242: ...and the generic names of the SCI I O pins The generic pin names appear in the text of this section 15 5 Functional Description Figure 15 1 shows the structure of the SCI module The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The transmitter and receiver of the SCI operate independently although they use the same baud rate gener...

Page 243: ... ILIE TE RE RWU SBK R8 T8 R ORIE FEIE PEIE BKF RPF SCI DATA RECEIVE SHIFT REGISTER SCIDATA REGISTER TRANSMIT SHIFT REGISTER NEIE M WAKE ILTY FLAG CONTROL TRANSMIT CONTROL RECEIVE CONTROL DATA SELECTION CONTROL WAKEUP PTY PEN REGISTER DMA INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL CONTROL R ENSCI LOOPS ENSCI PTE1 RxD PTE0 TxD INTERNAL BUS TXIN...

Page 244: ...0 0 0 0 0 0 0 0 0015 SCI Control Register 3 SCC3 Read R8 T8 R R ORIE NEIE FEIE PEIE Write Reset U U 0 0 0 0 0 0 0016 SCI Status Register 1 SCS1 Read SCTE TC SCRF IDLE OR NF FE PE Write Reset 1 1 0 0 0 0 0 0 0017 SCI Status Register 2 SCS2 Read BKF RPF Write Reset 0 0 0 0 0 0 0 0 0018 SCI Data Register SCDR Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6 T5 T4 T3 T2 T1 T0 Reset Unaffected by reset 0019 SC...

Page 245: ...ro mark space data format illustrated in Figure 15 3 Figure 15 3 SCI Data Formats 15 5 2 Transmitter Figure 15 4 shows the structure of the SCI transmitter BIT 5 START BIT BIT 0 BIT 1 NEXT STOP BIT START BIT 8 BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT BIT 0 NEXT STOP BIT START BIT 9 BIT DATA FORMAT BIT M IN SCC1 SET BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 2 BIT 3 BIT 4 BIT 6 BIT 7 ...

Page 246: ...11 BIT TRANSMIT STOP START T8 R SCTE SCTIE TCIE SBK TC PARITY GENERATION MSB SCI DATA REGISTER LOAD FROM SCDR SHIFT ENABLE PREAMBLE ALL 1s BREAK ALL 0s TRANSMITTER CONTROL LOGIC SHIFT REGISTER R TC SCTIE TCIE SCTE TRANSMITTER CPU INTERRUPT REQUEST TRANSMITTER DMA SERVICE REQUEST M ENSCI LOOPS TE PTE0 TxD TXINV INTERNAL BUS 4 PRE SCALER SCP1 SCP0 SCR2 SCR1 SCR0 BAUD DIVIDER 16 SCTIE CGMXCLK ...

Page 247: ...r empty bit by first reading SCI status register 1 SCS1 and then writing to the SCDR 4 Repeat step 3 for each subsequent transmission At the start of a transmission transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s After the preamble shifts out control logic transfers the SCDR data into the transmit shift register A logic 0 start bit automaticall...

Page 248: ...CI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be Receiving a break character has these effects on SCI registers Sets the framing error bit FE in SCS1 Sets the SCI receiver full bit SCRF in SCS1 Clears the SCI data register SCDR Clears the R8 bit in SCC3 Sets the break flag bit BKF in SCS2 May set the overrun ...

Page 249: ...tted data All transmitted values including idle break start and stop bits are inverted when TXINV is at logic 1 See 15 9 1 SCI Control Register 1 15 5 2 6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter SCI transmitter empty SCTE The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register SCTE can gene...

Page 250: ...iving 8 bit data bit R8 is a copy of the eighth bit bit 7 15 5 3 2 Character Reception During an SCI reception the receive shift register shifts characters in from the PTE1 RxD pin The SCI data register SCDR is the read only buffer between the internal data bus and the receive shift register After a complete character shifts into the receive shift register the data portion of the character transfe...

Page 251: ...N PTY BKF RPF H 8 7 6 5 4 3 2 1 0 L 11 BIT RECEIVE SHIFT REGISTER STOP START DATA RECOVERY R SCRF OR ORIE NF NEIE FE FEIE PE PEIE R SCRIE SCRF ILIE IDLE WAKEUP LOGIC PARITY CHECKING MSB ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST CPU INTERRUPT REQUEST SCI DATA REGISTER R8 R ORIE NEIE FEIE PEIE SCRIE ILIE RWU SCRF IDLE OR NF FE PE PTE1 RxD INTERNAL BUS PRE SCALER BAUD DIVIDER 4 16 SCP1 SCP0 SCR...

Page 252: ...ic 1 to logic 0 after the majority of data bit samples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 15 6 Receiver D...

Page 253: ...amples are logic 1s If start bit verification is not successful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 15 3 summarizes the results of the data bit samples Table 15 2 Start Bit Verification RT3 RT5 and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes ...

Page 254: ...does not detect a logic 1 where the stop bit should be in an incoming character it sets the framing error bit FE in SCS1 A break character also sets the FE bit because a break character has no stop bit The FE bit is set at the same time that the SCRF bit is set 15 5 3 5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit t...

Page 255: ...p bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 Figure 15 7 Slow Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 15 7 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit ...

Page 256: ...ror or a framing error The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8 RT9 and RT10 Figure 15 8 Fast Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 15 8 the receiver counts 154 RT cycles at the point when the count of...

Page 257: ...standby state during which receiver interrupts are disabled Depending on the state of the WAKE bit in SCC1 either of two conditions on the PTE1 RxD pin can bring the receiver out of the standby state Address mark An address mark is a logic 1 in the most significant bit position of a received character When the WAKE bit is set an address mark wakes the receiver from the standby state by clearing th...

Page 258: ... SCRIE in SCC2 enables the SCRF bit to generate receiver CPU interrupts Idle input IDLE The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the PTE1 RxD pin The idle line interrupt enable bit ILIE in SCC2 enables the IDLE bit to generate CPU interrupt requests 15 5 3 8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests Rece...

Page 259: ...odule remains active after the execution of a WAIT instruction In wait mode the SCI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction Refer to 8 7 Low Power Modes for in...

Page 260: ... break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit 15 8 I O Signals Port E shares two of its pins with the SCI module The two SCI I O pins are PTE0 T...

Page 261: ...ol register 1 SCC1 SCI control register 2 SCC2 SCI control register 3 SCC3 SCI status register 1 SCS1 SCI status register 2 SCS2 SCI data register SCDR SCI baud rate register SCBR 15 9 1 SCI Control Register 1 SCI control register 1 Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables par...

Page 262: ...nable SCI Bit This read write bit enables the SCI and the SCI baud rate generator Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts Reset clears the ENSCI bit 1 SCI enabled 0 SCI disabled TXINV Transmit Inversion Bit This read write bit reverses the polarity of transmitted data Reset clears the TXINV bit 1 Transmitter output inverted 0 Transmitte...

Page 263: ...ess mark wakeup 0 Idle line wakeup ILTY Idle Line Type Bit This read write bit determines when the SCI starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the stop bit may cause false recognition of an idle character Beginning the count after the stop bit avo...

Page 264: ...l Register 2 SCI control register 2 Enables the following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests Table 15 5 Character Format Selection Control Bits Char...

Page 265: ...smitter CPU interrupt requests Reset clears the TCIE bit 1 TC enabled to generate CPU interrupt requests 0 TC not enabled to generate CPU interrupt requests SCRIE SCI Receive Interrupt Enable Bit This read write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests Reset clears the SCRIE bit 1 SCRF enabled to generate CPU interrupt 0 SCRF not enabled to generate CPU interrupt IL...

Page 266: ...enabled 0 Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this read write bit enables the receiver Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Reset clears the RE bit 1 Receiver enabled 0 Receiver disabled NOTE Writing to the RE bit ...

Page 267: ... Transmit break characters 0 No break characters being transmitted NOTE Do not toggle the SBK bit immediately after setting the SCTE bit Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble 15 9 3 SCI Control Register 3 SCI control register 3 Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables these interrupt...

Page 268: ...quests generated by the receiver overrun bit OR 1 SCI error CPU interrupt requests from OR bit enabled 0 SCI error CPU interrupt requests from OR bit disabled NEIE Receiver Noise Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the noise error bit NE Reset clears NEIE 1 SCI error CPU interrupt requests from NE bit enabled 0 SCI error CPU interrup...

Page 269: ... SCTE SCI Transmitter Empty Bit This clearable read only bit is set when the SCDR transfers a character to the transmit shift register SCTE can generate an SCI transmitter CPU interrupt request When the SCTIE bit in SCC2 is set SCTE generates an SCI transmitter CPU interrupt request In normal operation clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR Reset sets the SCTE bi...

Page 270: ...nerates a CPU interrupt request In normal operation clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR Reset clears SCRF 1 Received data available in SCDR 0 Data not available in SCDR IDLE Receiver Idle Bit This clearable read only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input IDLE generates an SCI error CPU interrupt request if the ILIE bit in ...

Page 271: ...rrun and is lost The next flag clearing sequence reads byte 3 in the SCDR instead of byte 2 In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun the flag clearing routine can check the OR bit in a second read of SCS1 after reading the data register NF Receiver Noise Flag Bit This clearable read only bit is set when the SCI de...

Page 272: ... Clear the PE bit by reading SCS1 with PE set and then reading the SCDR Reset clears the PE bit 1 Parity error detected 0 No parity error detected BYTE 1 NORMAL FLAG CLEARING SEQUENCE READ SCS1 SCRF 1 READ SCDR BYTE 1 SCRF 1 SCRF 1 BYTE 2 BYTE 3 BYTE 4 OR 0 READ SCS1 SCRF 1 OR 0 READ SCDR BYTE 2 SCRF 0 READ SCS1 SCRF 1 OR 0 SCRF 1 SCRF 0 READ SCDR BYTE 3 SCRF 0 BYTE 1 READ SCS1 SCRF 1 READ SCDR BY...

Page 273: ...red BKF can become set again only after logic 1s again appear on the PTE1 RxD pin followed by another break character Reset clears the BKF bit 1 Break character detected 0 No break character detected RPF Reception in Progress Flag Bit This read only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search RPF does not generate an interrupt request RPF is re...

Page 274: ...ect on data in the SCI data register R7 T7 R0 T0 Receive Transmit Data Bits Reading address 0018 accesses the read only received data bits R7 R0 Writing to address 0018 writes the data to be transmitted T7 T0 Reset has no effect on the SCI data register NOTE Do not use read modify write instructions on the SCI data register Address 0018 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7...

Page 275: ...r Bits These read write bits select the baud rate prescaler divisor as shown in Table 15 6 Reset clears SCP1 and SCP0 SCR2 SCR0 SCI Baud Rate Select Bits These read write bits select the SCI baud rate divisor as shown in Table 15 7 Reset clears SCR2 SCR0 Address 0019 Bit 7 6 5 4 3 2 1 Bit 0 Read SCP1 SCP0 R SCR2 SCR1 SCR0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 15 16 SCI Baud R...

Page 276: ... CGMXCLK See 9 5 6 Crystal Output Frequency Signal CGMXCLK PD prescaler divisor BD baud rate divisor This makes the formula Table 15 8 shows the SCI baud rates that can be generated with a 4 9152MHz CGMXCLK Table 15 7 SCI Baud Rate Selection SCR2 SCR1 and SCR0 Baud Rate Divisor BD 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate SCI clock source 64 PD BD baud rate CGMXCLK 64 PD BD ...

Page 277: ...0 1 001 2 38 400 00 1 010 4 19 200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25 600 01 3 001 2 12 800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19 200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 590...

Page 278: ...Serial Communications Interface Technical Data MC68HC908AB32 Rev 1 0 278 Serial Communications Interface Module SCI MOTOROLA ...

Page 279: ...ransmission Formats 285 16 6 1 Clock Phase and Polarity Controls 285 16 6 2 Transmission Format When CPHA 0 286 16 6 3 Transmission Format When CPHA 1 288 16 6 4 Transmission Initiation Latency 289 16 7 Queuing Transmission Data 291 16 8 Error Conditions 292 16 8 1 Overflow Error 292 16 8 2 Mode Fault Error 294 16 9 Interrupts 296 16 10 Resetting the SPI 298 16 11 Low Power Modes 299 16 11 1 Wait ...

Page 280: ...ipheral devices 16 3 Features Features of the SPI module include the following Full duplex operation Master and slave modes Double buffered operation with separate transmit and receive registers Four master mode frequencies maximum bus frequency 2 Maximum slave mode frequency bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts SPRF SPI receiver full SP...

Page 281: ... appear in the text that follows 16 5 Functional Description Figure 16 1 summarizes the SPI I O registers and Figure 16 2 shows the structure of the SPI module Table 16 1 Pin Name Conventions SPI Generic Pin Names MISO MOSI SS SPSCK CGND Full SPI Pin Names SPI PTE5 MISO PTE6 MOSI PTE4 SS PTE7 SPSCK VSS Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 0010 SPI Control Register SPCR Read SPRIE R SPMSTR CP...

Page 282: ...PI status flags or SPI operation can be interrupt driven The following paragraphs describe the operation of the SPI module TRANSMITTER CPU INTERRUPT REQUEST RESERVED RECEIVER ERROR CPU INTERRUPT REQUEST 7 6 5 4 3 2 1 0 SPR1 SPMSTR TRANSMIT DATA REGISTER SHIFT REGISTER SPR0 CGMOUT 2 CLOCK SELECT 2 CLOCK DIVIDER 8 32 128 CLOCK LOGIC CPHA CPOL SPI SPRIE R SPE SPWOM SPRF SPTE OVRF RESERVED M S PIN CON...

Page 283: ...isabling the master SPI See 16 14 1 SPI Control Register Only a master SPI module can initiate transmissions Software begins the transmission from a master SPI module by writing to the transmit data register If the shift register is empty the byte immediately transfers to the shift register setting the SPI transmitter empty bit SPTE The byte begins shifting out on the MOSI pin under the control of...

Page 284: ...de when the SPMSTR bit is clear In slave mode the SPSCK pin is the input for the serial clock from the master MCU Before a data transmission occurs the SS pin of the slave SPI must be at logic 0 SS must remain low until the transmission is complete See 16 8 2 Mode Fault Error In a slave SPI module data enters the shift register under the control of the serial clock from the master SPI module After...

Page 285: ...r the falling edge of SS starts a transmission See 16 6 Transmission Formats NOTE SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge 16 6 Transmission Formats During an SPI transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock synchronizes shifting and sampling on the two ...

Page 286: ...her for CPOL 1 The diagram may be interpreted as a master or slave timing diagram since the serial clock SPSCK master in slave out MISO and master out slave in MOSI pins are directly connected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MIS...

Page 287: ...egins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the falling edge of SS Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 B...

Page 288: ...input to the slave The slave SPI drives its MISO output only when its slave select input SS is at logic 0 so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose I O not affecting the SPI See 16 8 2 Mode Fault Error When CPHA 1 the master begins driving ...

Page 289: ...y to the start of the transmission but it does affect the initial state of the SPSCK signal When CPHA 0 the SPSCK signal remains inactive for the first half of the first SPSCK cycle When CPHA 1 the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level The SPI clock rate selected by SPR1 SPR0 affects the delay from the write to SPDR and the start of the SPI t...

Page 290: ...CYCLE NUMBER MSB BIT 6 1 2 CLOCK WRITE TO SPDR EARLIEST LATEST SPSCK INTERNAL CLOCK 2 EARLIEST LATEST 2 POSSIBLE START POINTS SPSCK INTERNAL CLOCK 8 8 POSSIBLE START POINTS EARLIEST LATEST SPSCK INTERNAL CLOCK 32 32 POSSIBLE START POINTS EARLIEST LATEST SPSCK INTERNAL CLOCK 128 128 POSSIBLE START POINTS WRITE TO SPDR WRITE TO SPDR WRITE TO SPDR BUS CLOCK BIT 5 3 BUS CLOCK BUS CLOCK BUS CLOCK INITI...

Page 291: ...no new data is written to the data buffer the last value contained in the shift register is the next data word to be transmitted BIT 3 MOSI SPSCK SPTE WRITE TO SPDR 1 CPU WRITES BYTE 2 TO SPDR QUEUEING BYTE 2 CPU WRITES BYTE 1 TO SPDR CLEARING SPTE BIT BYTE 1 TRANSFERS FROM TRANSMIT DATA 3 1 2 2 3 5 REGISTER TO SHIFT REGISTER SETTING SPTE BIT SPRF READ SPSCR MSB BIT 6 BIT 5 BIT 4 BIT 2 BIT 1 LSBMS...

Page 292: ...s in the SPI status and control register Mode fault error MODF The MODF bit indicates that the voltage on the slave select pin SS is inconsistent with the mode of the SPI MODF is in the SPI status and control register 16 8 1 Overflow Error The overflow flag OVRF becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next ...

Page 293: ...on In this case an overflow can be missed easily Since no more SPRF interrupts can be generated until this OVRF is serviced it is not obvious that bytes are being lost as more transmissions are completed To prevent this either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR This ensures that the OVRF was not set before the SPRF was cleared and that future t...

Page 294: ...ansmission The SS pin of a master SPI goes low at any time For the MODF flag to be set the mode fault error enable bit MODFEN must be set Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared READ READ OVRF SPRF BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 BYTE 1 SETS SPRF BIT CPU READS SPSCR WITH SPRF BIT SET CPU READS BYTE 1 IN SPDR CPU READS SPSC...

Page 295: ...hared I O port regains control of port drivers NOTE To prevent bus contention with another master SPI after a mode fault error clear all SPI bits of the data direction register of the shared I O port before enabling the SPI When configured as a slave SPMSTR 0 the MODF flag is set if SS goes high during a transmission When CPHA 0 a transmission begins when SS goes low and ends once the incoming SPS...

Page 296: ...ission by clearing the SPE bit of the slave NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state Also the slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmission To clear the MODF flag read the SPSCR with the MODF bit set and then write to the SPCR register This entire clearing mechanism must occur with no MODF c...

Page 297: ...PI is enabled SPE 1 The SPI receiver interrupt enable bit SPRIE enables the SPRF bit to generate receiver CPU interrupt requests regardless of the state of the SPE bit See Figure 16 11 The error interrupt enable bit ERRIE enables both the MODF and OVRF bits to generate a receiver error CPU interrupt request The mode fault enable bit MODFEN can prevent the MODF flag from being set so that only the ...

Page 298: ...IE is also set SPTE generates an SPTE CPU interrupt request 16 10 Resetting the SPI Any system reset completely resets the SPI Partial resets occur whenever the SPI enable bit SPE is low Whenever SPE is low the following occurs The SPTE flag is set Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared making it ready for a new complete tra...

Page 299: ...r the execution of a WAIT instruction In wait mode the SPI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode If SPI module functions are not required during wait mode reduce power consumption by disabling the SPI module before executing the WAIT instruction To exit wait mode when an overflow condition occurs enab...

Page 300: ...With BCFE at logic 0 its default state software can read and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit Since t...

Page 301: ...r SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin Slave output data on the MISO pin is enabled only when the SPI is configured as a slave The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0 To support a multiple slave system a logic 1 on the SS pin puts the MISO pin in a high impedance state When enabled the SPI control...

Page 302: ... slave For CPHA 0 the SS is used to define the start of a transmission See 16 6 Transmission Formats Since it is used to indicate the start of a transmission the SS must be toggled high and low between each byte transmitted for the CPHA 0 format However it can remain low between transmissions for the CPHA 1 format See Figure 16 12 Figure 16 12 CPHA SS Timing When an SPI is configured as a slave th...

Page 303: ...hared I O port With MODFEN high it is an input only pin to the SPI regardless of the state of the data direction register of the shared I O port The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register See Table 16 3 16 13 5 CGND Clock Ground CGND is the ground return for the serial clock pin SPSCK and the ground for the port...

Page 304: ...ave Selects serial clock polarity and phase Configures the SPSCK MOSI and MISO pins as open drain outputs Enables the SPI module SPRIE SPI Receiver Interrupt Enable Bit This read write bit enables CPU interrupt requests generated by the SPRF bit The SPRF bit is set when a byte transfers from the shift register to the receive data register Reset clears the SPRIE bit 1 SPRF CPU interrupt requests en...

Page 305: ...I modules the SPI modules must have identical CPHA values When CPHA 0 the SS pin of the slave SPI module must be set to logic 1 between bytes See Figure 16 12 Reset sets the CPHA bit SPWOM SPI Wired OR Mode Bit This read write bit disables the pullup devices on pins SPSCK MOSI and MISO so that those pins become open drain outputs 1 Wired OR SPSCK MOSI and MISO pins 0 Normal push pull SPSCK MOSI an...

Page 306: ...terrupts Enable mode fault error detection Select master SPI baud rate SPRF SPI Receiver Full Bit This clearable read only flag is set each time a byte transfers from the shift register to the receive data register SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also During an SPRF CPU interrupt the CPU clears SPRF by reading the SPI status and control re...

Page 307: ...lears the OVRF bit 1 Overflow 0 No overflow MODF Mode Fault Bit This clearable read only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set In a master SPI the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set Clear the MODF bit by reading the SPI status and control register SPSCR with MODF set and then writing to the SPI cont...

Page 308: ...alue of MODFEN See 16 13 4 SS Slave Select If the MODFEN bit is low the level of the SS pin does not affect the operation of an enabled SPI configured as a master For an enabled SPI configured as a slave having MODFEN low only prevents the MODF flag from being set It does not affect any other part of SPI operation See 16 8 2 Mode Fault Error SPR1 and SPR0 SPI Baud Rate Select Bits In master mode t...

Page 309: ...mit data register Reading the SPI data register reads data from the receive data register The transmit data and receive data registers are separate registers that can contain different values See Figure 16 2 R7 R0 T7 T0 Receive Transmit Data Bits NOTE Do not use read modify write instructions on the SPI data register since the register read is not the same as the register written Address 0012 Bit ...

Page 310: ...Serial Peripheral Interface Module SPI Technical Data MC68HC908AB32 Rev 1 0 310 Serial Peripheral Interface Module SPI MOTOROLA ...

Page 311: ... 2 Data Direction Register C DDRC 321 17 6 Port D 323 17 6 1 Port D Data Register PTD 323 17 6 2 Data Direction Register D DDRD 324 17 6 3 Port D Input Pullup Enable Register PTDPUE 325 17 7 Port E 326 17 7 1 Port E Data Register PTE 326 17 7 2 Data Direction Register E DDRE 328 17 8 Port F 329 17 8 1 Port F Data Register PTF 329 17 8 2 Data Direction Register F DDRF 330 17 8 3 Port F Input Pullup...

Page 312: ... reset 0001 Port B Data Register PTB Read PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write Reset Unaffected by reset 0002 Port C Data Register PTC Read 0 0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Write Reset Unaffected by reset 0003 Port D Data Register PTD Read PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write Reset Unaffected by reset 0004 Data Direction Register A DDRA Read DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 D...

Page 313: ...E7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 Write Reset 0 0 0 0 0 0 0 0 000D Data Direction Register F DDRF Read DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 Write Reset 0 0 0 0 0 0 0 0 000E Data Direction Register G DDRG Read 0 0 0 0 0 DDRG2 DDRG1 DDRG0 Write Reset 0 0 0 0 0 0 0 0 000F Data Direction Register H DDRH Read 0 0 0 0 0 0 DDRH1 DDRH0 Write Reset 0 0 0 0 0 0 0 0 003D Port D Input Pu...

Page 314: ... PTA4 5 DDRA5 PTA5 6 DDRA6 PTA6 7 DDRA7 PTA7 B 0 DDRB0 ADC ADSCR 0038 ADCH 4 0 PTB0 ATD0 1 DDRB1 PTB1 ATD1 2 DDRB2 PTB2 ATD2 3 DDRB3 PTB3 ATD3 4 DDRB4 PTB4 ATD4 5 DDRB5 PTB5 ATD5 6 DDRB6 PTB6 ATD6 7 DDRB7 PTB7 ATD7 C 0 DDRC0 PTC0 1 DDRC1 PTC1 2 DDRC2 DDRC 0006 MCLKEN PTC2 MCLK 3 DDRC3 PTC3 4 DDRC4 PTC4 5 DDRC5 PTC5 D 0 DDRD0 PTD0 1 DDRD1 PTD1 2 DDRD2 PTD2 3 DDRD3 PTD3 4 DDRD4 TIMB TBSC 0040 PS 2 0...

Page 315: ...SCK F 0 DDRF0 TIMA TASC2 002C ELS2B ELS2A PTF0 TACH2 1 DDRF1 TASC3 002F ELS3B ELS3A PTF1 TACH3 2 DDRF2 TIMB TBSC2 0032 ELS2B ELS2A PTF2 TBCH2 3 DDRF3 TBSC3 0035 ELS3B ELS3A PTF3 TBCH3 4 DDRF4 TBSC0 0045 ELS0B ELS0A PTF4 TBCH0 5 DDRF5 TBSC1 0048 ELS1B ELS1A PTF5 TBCH1 6 DDRF6 PTF6 7 DDRF7 PTF7 G 0 DDRG0 KBI KBIER 0021 KBIE0 PTG0 KBD0 1 DDRG1 KBIE1 PTG1 KBD1 2 DDRG2 KBIE2 PTG2 KBD2 H 0 DDRH0 KBIE3 P...

Page 316: ...it in data direction register A Reset has no effect on port A data 17 3 2 Data Direction Register A DDRA Data direction register A determines whether each port A pin is an input or an output Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin a logic 0 disables the output buffer Address 0000 Bit 7 6 5 4 3 2 1 Bit 0 Read PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0...

Page 317: ...c Figure 17 4 Port A I O Circuit When DDRAx is a logic 1 reading address 0000 reads the PTAx data latch When DDRAx is a logic 0 reading address 0000 reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 17 2 summarizes the operation of the port A pins Table 17 2 Port A Pin Functions DDRA Bit PTA Bit I O Pin Mode Accesses to ...

Page 318: ...ns used for the input channels to the analog to digital converter module The channel select bits in the ADC status and control register define which port B pin will be used as an ADC input and overrides any control from the port I O logic by forcing that pin as the input to the analog circuitry NOTE Care must be taken when reading port B while applying analog voltages to ATD 7 0 pins If the approp...

Page 319: ...Reset clears DDRB 7 0 configuring all port B pins as inputs 1 Corresponding port B pin configured as output 0 Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1 Figure 17 7 shows the port B I O logic Figure 17 7 Port B I O Circuit Address 0005 Bit 7 6 5 4 3 2 1 Bit 0 Read ...

Page 320: ... port PTC2 pin can be configured as an output pin for the system MCLK clock 17 5 1 Port C Data Register PTC The port C data register contains a data latch for each of the six port C pins Table 17 3 Port B Pin Functions DDRB Bit PTB Bit I O Pin Mode Accesses to DDRB Accesses to PTB Read Write Read Write 0 X 1 Notes 1 X don t care Input Hi Z 2 2 Hi Z high impedance DDRB 7 0 Pin PTB 7 0 3 3 Writing a...

Page 321: ...pin a logic 0 disables the output buffer MCLKEN T12 System Clock Enable Bit This read write bit enables MCLK to be an output signal on PTC2 pin Reset clears MCLKEN 1 PTC2 pin configured as MCLK output 0 PTC2 pin configured as standard I O pin DDRC 5 0 Data Direction Register C Bits These read write bits control port C data direction Reset clears DDRC 5 0 configuring all port C pins as inputs 1 Cor...

Page 322: ...ta direction bit Table 17 4 summarizes the operation of the port C pins Table 17 4 Port C Pin Functions DDRC Bit PTC Bit I O Pin Mode Accesses to DDRC Accesses to PTC Read Write Read Write 0 2 Input Hi Z DDRC7 Pin PTC2 1 2 Output DDRC7 0 0 X 1 Notes 1 X don t care except PTC2 Input Hi Z 2 2 Hi Z high impedance DDRC 5 0 Pin PTC 5 0 3 3 Writing affects data register but does not affect input 1 X Out...

Page 323: ...onding bit in data direction register D Reset has no effect on port D data TACLK Timer A Clock Input The PTD6 pin becomes TACLK the timer A TIMA external clock input when the TIMA prescaler select bits PS 2 0 111 See Section 11 Timer Interface Module A TIMA TBCLK Timer B Clock Input The PTD4 pin becomes TBCLK the timer B TIMB external clock input when the TIMB prescaler select bits PS 2 0 111 See ...

Page 324: ...7 0 configuring all port D pins as inputs 1 Corresponding port D pin configured as output 0 Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1 Figure 17 13 shows the port D I O logic Figure 17 13 Port D I O Circuit Address 0007 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRD7 DDRD6 DDRD...

Page 325: ...red as an input Each pullup is automatically and dynamically disabled when a port bit s DDRD is configured for output mode PTDPUE 7 0 Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port pin 1 Corresponding port D pin configured to have internal pullup 0 Corresponding port D pin internal pullup disconnected Table 17 5 Port D Pin Fu...

Page 326: ...er the control of the corresponding bit in data direction register E Reset has no effect on port E data SPSCK SPI Serial Clock The PTE7 SPSCK pin is the serial clock input of a SPI slave module and serial clock output of a SPI master modules When the SPE bit is clear the PTE7 SPSCK pin is available for general purpose I O See 16 14 1 SPI Control Register MOSI Master Out Slave In The PTE6 MOSI pin ...

Page 327: ...output compare pins The edge level select bits ELSxB ELSxA determine whether the PTE3 TACH1 PTE2 TACH0 pins are timer channel I O pins or general purpose I O pins See 11 10 4 TIMA Channel Status and Control Registers RxD SCI Receive Data Input The PTE1 RxD pin is the receive data input for the SCI module When the enable SCI bit ENSCI is clear the SCI module is disabled and the PTE1 RxD pin is avai...

Page 328: ...direction Reset clears DDRE 7 0 configuring all port E pins as inputs 1 Corresponding port E pin configured as output 0 Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1 Figure 17 17 shows the port E I O logic Figure 17 17 Port E I O Circuit Address 000C Bit 7 6 5 4 3 2 1...

Page 329: ...t F Data Register PTF The port F data register contains a data latch for each of the eight port F pins Table 17 6 Port E Pin Functions DDRE Bit PTE Bit I O Pin Mode Accesses to DDRE Accesses to PTE Read Write Read Write 0 X 1 Notes 1 X don t care Input Hi Z 2 2 Hi Z high impedance DDRE 7 0 Pin PTE 7 0 3 3 Writing affects data register but does not affect the input 1 X Output DDRE 7 0 PTE 7 0 PTE 7...

Page 330: ...irection register F DDRF does not affect the data direction of port F pins that are being used by TIMA and TIMB However the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins See Table 17 7 17 8 2 Data Direction Register F DDRF Data direction register F determines whether each port F pin is an input or an output Writing a logic 1 to a DDRF...

Page 331: ...pin The data latch can always be written regardless of the state of its data direction bit Table 17 7 summarizes the operation of the port F pins Table 17 7 Port F Pin Functions DDRF Bit PTF Bit I O Pin Mode Accesses to DDRF Accesses to PTF Read Write Read Write 0 X 1 Notes 1 X don t care Input Hi Z 2 2 Hi Z high impedance DDRF 7 0 Pin PTF 7 0 3 3 Writing affects data register but does not affect ...

Page 332: ...e PTFPUE 7 0 Port F Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port pin 1 Corresponding port F pin configured to have internal pullup 0 Corresponding port F pin internal pullup disconnected 17 9 Port G Port G is a 3 bit special function port that shares all three of its pins with the keyboard interrupt KBI module 17 9 1 Port G Data R...

Page 333: ...ins as external interrupt pins See Section 19 Keyboard Interrupt Module KBI 17 9 2 Data Direction Register G DDRG Data direction register G determines whether each port G pin is an input or an output Writing logic 1 to a DDRG bit enables the output buffer for the corresponding port G pin a logic 0 disables the output buffer Address 000A Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 PTG2 PTG1 PTG0 Write R...

Page 334: ...e 17 24 Port G I O Circuit When DDRGx is a logic 1 reading address 000A reads the PTGx data latch When DDRGx is a logic 0 reading address 000A reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 17 6 summarizes the operation of the port G pins Table 17 8 Port G Pin Functions DDRG Bit PTG Bit I O Pin Mode Accesses to DDRG A...

Page 335: ...ponding bit in data direction register H Reset has no effect on port H data KBD 4 3 The keyboard interrupt enable bits KBIE 4 3 in the keyboard interrupt enable register KBIER enable the port H pins as external interrupt pins See Section 19 Keyboard Interrupt Module KBI 17 10 2 Data Direction Register H DDRH Data direction register H determines whether each port H pin is an input or an output Writ...

Page 336: ...rection register H bits from 0 to 1 Figure 17 27 shows the port H I O logic Figure 17 27 Port H I O Circuit When DDRHx is a logic 1 reading address 000B reads the PTHx data latch When DDRHx is a logic 0 reading address 000B reads the voltage level on the pin The data latch can always be written regardless of the state of its data direction bit Table 17 6 summarizes the operation of the port H pins...

Page 337: ...37 Table 17 9 Port H Pin Functions DDRH Bit PTH Bit I O Pin Mode Accesses to DDRH Accesses to PTH Read Write Read Write 0 X 1 Input Hi Z 2 DDRH 1 0 Pin PTH 1 0 3 1 X Output DDRH 1 0 PTH 1 0 PTH 1 0 Notes 1 X don t care 2 Hi Z high impedance 3 Writing affects data register but does not affect the input ...

Page 338: ...Input Output I O Ports Technical Data MC68HC908AB32 Rev 1 0 338 Input Output I O Ports MOTOROLA ...

Page 339: ...8 5 IRQ Status and Control Register ISCR 343 18 6 IRQ Module During Break Interrupts 344 18 2 Introduction The IRQ external interrupt module provides a maskable interrupt input 18 3 Features Features of the IRQ module include the following A dedicated external interrupt pin IRQ IRQ interrupt control bits Hysteresis buffer Programmable edge only or edge and level interrupt sensitivity Automatic int...

Page 340: ...ng edge triggered and is software configurable to be either falling edge or falling edge and low level triggered The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin When the interrupt pin is edge triggered only the CPU interrupt request remains set until a vector fetch software clear or reset occurs When the interrupt pin is both falling edge and low level triggered the CPU...

Page 341: ...trol Figure 18 1 IRQ Module Block Diagram ACK IMASK D Q CK CLR IRQ HIGH INTERRUPT TO MODE SELECT LOGIC IRQ FF REQUEST VDD MODE VOLTAGE DETECT SYNCHRO NIZER IRQF TO CPU FOR BIL BIH INSTRUCTIONS VECTOR FETCH DECODER INTERNAL ADDRESS BUS RESET VDD INTERNAL PULLUP DEVICE IRQ Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 001A IRQ Status and Control Register ISCR Read 0 0 0 0 IRQF 0 IMASK MODE Write ACK Re...

Page 342: ... IRQ pin A falling edge that occurs after writing to the ACK bit latches another interrupt request If the IRQ mask bit IMASK is clear the CPU loads the program counter with the vector address at locations FFFA and FFFB Return of the IRQ pin to logic 1 As long as the IRQ pin is at logic 0 IRQ remains active The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any...

Page 343: ... IRQ interrupt not pending ACK IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write only bit clears the IRQ latch ACK always reads as logic 0 Reset clears ACK IMASK IRQ Interrupt Mask Bit Writing a logic 1 to this read write bit disables IRQ interrupt requests Reset clears IMASK 1 IRQ interrupt requests disabled 0 IRQ interrupt requests enabled MODE IRQ Edge Level Select Bit This ...

Page 344: ...clear the latches during the break state See Section 8 System Integration Module SIM To allow software to clear the IRQ latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect the latches during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state w...

Page 345: ...ns 346 19 5 Functional Description 347 19 5 1 Keyboard Initialization 349 19 5 2 Keyboard Status and Control Register 349 19 5 3 Keyboard Interrupt Enable Register 351 19 6 Wait Mode 351 19 7 Stop Mode 351 19 8 Keyboard Module During Break Interrupts 352 19 2 Introduction The keyboard interrupt module KBI provides five independently maskable external interrupts which are accessible via PTG0 PTG2 a...

Page 346: ...upt pins are shared with standard port I O pins The full name of the KBI pins are listed in Table 19 1 The generic pin name appear in the text that follows Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 001B Keyboard Status and Control Register KBSCR Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 0021 Keyboard Interrupt Enable Register KBIER Read 0 0 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 ...

Page 347: ...ontrol register controls the triggering mode of the keyboard interrupt If the keyboard interrupt is edge sensitive only a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low To prevent losing an interrupt request on one pin because another pin is still low software can disable the latter pin while it is low If the keyboard interrupt is falling ...

Page 348: ...ny enabled keyboard interrupt pin is at logic 0 the keyboard interrupt remains set The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order If the MODEK bit is clear the keyboard interrupt pin is falling edge sensitive only With MODEK clear a vector fetch or software clear immediately clears the keyboard interrupt request Reset clea...

Page 349: ...status and control register to clear any false interrupts 4 Clear the IMASKK bit An interrupt signal on an edge triggered pin can be acknowledged immediately after enabling the pin An interrupt signal on an edge and level triggered interrupt pin must be acknowledged after a delay that depends on the external load Another way to avoid a false interrupt 1 Configure the keyboard pins as outputs by se...

Page 350: ... IMASKK Keyboard Interrupt Mask Bit Writing a logic 1 to this read write bit prevents the output of the keyboard interrupt mask from generating interrupt requests Reset clears the IMASKK bit 1 Keyboard interrupt requests masked 0 Keyboard interrupt requests not masked MODEK Keyboard Triggering Sensitivity Bit This read write bit controls the triggering sensitivity of the keyboard interrupt pins Re...

Page 351: ...enabled as keyboard interrupt pin 0 KBDx pin not enabled as keyboard interrupt pin 19 6 Wait Mode The keyboard modules remain active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode 19 7 Stop Mode The keyboard module remains active in stop mode Clearing the IMASKK bit in the keyboard status and co...

Page 352: ...r BFCR enables software to clear status bits during the break state To allow software to clear the keyboard interrupt latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect the latch during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state writi...

Page 353: ...tch 356 20 4 7 COPD COP Disable 356 20 4 8 COPRS COP Rate Select 356 20 5 COP Control Register 357 20 6 Interrupts 357 20 7 Monitor Mode 357 20 8 Low Power Modes 357 20 8 1 Wait Mode 358 20 8 2 Stop Mode 358 20 9 COP Module During Break Mode 358 20 2 Introduction The computer operating properly COP module contains a free running counter that generates a reset if allowed to overflow The COP module ...

Page 354: ... CGMXCLK cycle overflow option a 4 9152MHz crystal gives a COP timeout period of 53 3ms Writing any value to location FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow C...

Page 355: ... the COP from generating a reset even while the main program is not working properly 20 4 I O Signals The following paragraphs describe the signals shown in Figure 20 1 20 4 1 CGMXCLK CGMXCLK is the crystal oscillator output signal CGMXCLK frequency is equal to the crystal frequency 20 4 2 STOP Instruction The STOP instruction clears the COP prescaler 20 4 3 COPCTL Write Writing any value to the C...

Page 356: ... in the configuration register 1 See Figure 20 2 20 4 8 COPRS COP Rate Select The COPRS signal reflects the state of the COP rate select bit COPRS in the configuration register 1 See Figure 20 2 COPRS COP Rate Select Bit COPRS selects the COP timeout period Reset clears COPRS 1 COP timeout period is 218 24 CGMXCLK cycles 0 COP timeout period is 213 24 CGMXCLK cycles COPD COP Disable Bit COPD disab...

Page 357: ...s The COP does not generate CPU interrupt requests 20 7 Monitor Mode When monitor mode is entered with VTST on the IRQ pin the COP is disabled as long as VTST remains on the IRQ pin or the RST pin When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin the COP is automatically disabled until a POR occurs 20 8 Low Power Modes The WAIT and STOP instructions put ...

Page 358: ...prescaler Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode To prevent inadvertently turning off the COP with a STOP instruction a configuration option is available that disables the STOP instruction When the STOP bit in the configuration register has the STOP instruction is disabled execution of a STOP in...

Page 359: ... 4 3 False Reset Protection 361 21 5 LVI Status Register LVISR 362 21 6 LVI Interrupts 362 21 7 Low Power Modes 363 21 7 1 Wait Mode 363 21 7 2 Stop Mode 363 21 2 Introduction This section describes the low voltage inhibit module which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage 21 3 Features Features of the LVI module include the fo...

Page 360: ...ster 1 CONFIG1 See Section 6 Configuration Register CONFIG for details of the LVI s configuration bits Once an LVI reset occurs the MCU remains in reset until VDD rises above a voltage LVITRIPR which causes the MCU to exit reset See 8 4 2 5 Low Voltage Inhibit LVI Reset for details of the interaction between the SIM and the LVI The output of the comparator controls the state of the LVIOUT flag in ...

Page 361: ...ows the LVI module to reset the MCU when VDD falls below the LVITRIPF level and remains at or below that level for 9 or more consecutive CPU cycles In configuration register 1 the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets 21 4 3 False Reset Protection The VDD pin level is digitally filtered to reduce false resets due to power supply noise In orde...

Page 362: ...cycles See Table 21 1 Reset clears the LVIOUT bit 21 6 LVI Interrupts The LVI module does not generate interrupt requests Address FE0F Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 21 3 LVI Status Register LVISR Table 21 1 LVIOUT Bit Indication VDD LVIOUT At level For number of CGMXCLK cycles VDD LVITRIPR Any 0 VDD LVITRIPF 32 CGMXCLK cycles 0 V...

Page 363: ...onsumption standby modes 21 7 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of wait mode 21 7 2 Stop Mode If enabled in stop mode LVISTOP set the LVI module remains active in stop mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of stop mode ...

Page 364: ...Low Voltage Inhibit LVI Technical Data MC68HC908AB32 Rev 1 0 364 Low Voltage Inhibit LVI MOTOROLA ...

Page 365: ...TIMB During Break Interrupts 368 22 4 4 COP During Break Interrupts 368 22 5 Low Power Modes 368 22 5 1 Wait Mode 368 22 5 2 Stop Mode 369 22 6 Break Module Registers 369 22 6 1 Break Status and Control Register 369 22 6 2 Break Address Registers 370 22 6 3 SIM Break Status Register 370 22 6 4 SIM Break Flag Control Register 372 22 2 Introduction This section describes the break module BRK The bre...

Page 366: ... interrupt instruction SWI after completion of the current CPU instruction The program counter vectors to FFFC and FFFD FEFC and FEFD in monitor mode The following events can cause a break interrupt to occur A CPU generated address the address in the program counter matches the contents of the break address registers Software writes a logic 1 to the BRKA bit in the break status and control registe...

Page 367: ...ister SBSR Read R R R R R R SBSW R Write Note Reset 0 0 0 0 0 0 0 0 FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write Reset 0 FE0C Break Address Register High BRKH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 FE0D Break Address Register Low BRKL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 FE0E Break Status and Control Register BRKSCR Read BRKE ...

Page 368: ... instruction in progress If the break address register match occurs on the last cycle of a CPU instruction the break interrupt begins immediately 22 4 3 PIT TIMA and TIMB During Break Interrupts A break interrupt stops all timer counters 22 4 4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin 22 5 Low Power Modes The WAIT and STOP instruc...

Page 369: ...r low BRKL SIM Break status register SBSR SIM Break flag control register SBFCR 22 6 1 Break Status and Control Register The break status and control register BRKSCR contains break module enable and status bits BRKE Break Enable Bit This read write bit enables breaks on break address register matches Clear BRKE by writing a logic 0 to bit 7 Reset clears the BRKE bit 1 Breaks enabled on 16 bit addr...

Page 370: ...registers BRKH and BRKL contain the high and low bytes of the desired breakpoint address Reset clears the break address registers 22 6 3 SIM Break Status Register The SIM break status register SBSR contains a flag to indicate that a break caused an exit from wait mode The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt Address FE0C Bit 7 6 5 4 3 ...

Page 371: ...btracting one from it The following code is an example Address FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read R R R R R R SBSW R Write Note Reset 0 0 0 0 0 0 0 0 Note Writing a logic 0 clears SBSW R Reserved Figure 22 6 SIM Break Status Register SBSR This code works if the H register has been pushed onto the stack in the break service routine software This code should be executed at the end of the break servic...

Page 372: ...reak state BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved F...

Page 373: ...ctrical Characteristics 376 23 7 EEPROM and Memory Characteristics 377 23 8 5 0 V Control Timing 378 23 9 Timer Interface Module Characteristics 378 23 10 ADC Characteristics 379 23 11 SPI Characteristics 380 23 12 Clock Generation Module Characteristics 383 23 12 1 CGM Operating Conditions 383 23 12 2 CGM Component Information 383 23 12 3 CGM Acquisition Lock Time Information 384 23 13 FLASH Memo...

Page 374: ...at normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that VIn and VOut be constrained to the range VSS VIn or VOut VDD Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either VSS or VDD Characteristic 1 Notes 1 V...

Page 375: ...ange VDD 5 0 10 5 0 10 V Characteristic Symbol Value Unit Thermal resistance QFP 64 pin θJA 70 C W I O pin power dissipation PI O User Determined W Power dissipation 1 Notes 1 Power dissipation is a function of temperature PD PD IDD VDD PI O K TJ 273 C W Constant 2 2 K is a constant unique to the device K can be determined for a known TA and measured PD With this value of K PD and TJ can be determ...

Page 376: ...PTD7 only Maximum combined IOL for port C port E port F port G port H Maximum combined IOL for port D port A port B Maximum total IOL for all port pins VOL VOL VOL IOL1 IOL2 IOLT 0 4 1 5 1 0 50 50 100 V V V mA mA mA Input high voltage All ports IRQ RST OSC1 VIH 0 7 VDD VDD V Input low voltage All ports IRQ RST OSC1 VIL VSS 0 3 VDD V VDD supply current Run 3 Wait 4 Stop 5 LVI enabled TA 25 C LVI di...

Page 377: ...gured as inputs OSC2 capacitance linearly affects wait IDD Measured with PLL and LVI enabled 5 Stop IDD is measured with OSC1 VSS 6 Pullups are disabled Port B leakage is specified in 23 10 ADC Characteristics 7 Maximum is highest voltage that POR is guaranteed 8 Maximum is highest voltage that POR is possible 9 If minimum VDD is not reached before the internal POR reset is released RST must be dr...

Page 378: ...Hz RESET input pulse width low 6 6 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset tIRL 1 5 tcyc IRQ interrupt pulse width low 7 Edge triggered 7 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized tILIH 1 5 tcyc IRQ interrupt pulse period tILIL Note 8 8 Minimum pulse width is f...

Page 379: ...ly at 1 MHz Conversion range RAD VREFL VREFH V VREFL VSSA Power up time tADPU 16 tAIC cycles Conversion time tADC 16 17 tAIC cycles Sample time 2 tADS 5 tAIC cycles Zero input reading 3 ZADI 00 01 Hex VIN VREFL Full scale reading 3 FADI FE FF Hex VIN VREFH Input capacitance CADI 20 8 pF Not tested Input leakage 4 Port B 1 µA Notes 1 VDD 5 0 Vdc 10 VDDA VDDAREF 5 0 Vdc 10 VREFH 5 0 Vdc 10 VSS 0 Vdc...

Page 380: ... 2 Enable lead time tLead S 15 ns 3 Enable lag time tLag S 15 ns 4 Clock SPSCK high time Master Slave tSCKH M tSCKH S 100 50 ns ns 5 Clock SPSCK low time Master Slave tSCKL M tSCKL S 100 50 ns ns 6 Data setup time inputs Master Slave tSU M tSU S 45 5 ns ns 7 Data hold time inputs Master Slave tH M tH S 0 15 ns ns 8 Access time slave 3 CPHA 0 CPHA 1 3 Time to data active from high impedance state t...

Page 381: ...NPUT SPSCK OUTPUT SPSCK OUTPUT MISO INPUT MOSI OUTPUT NOTE 4 5 5 1 4 BITS 6 1 LSB IN MASTER MSB OUT BITS 6 1 MASTER LSB OUT 11 10 11 7 6 NOTE Note This last clock edge is generated internally but is not seen at the SPSCK pin SS PIN OF MASTER HELD HIGH MSB IN SS INPUT SPSCK OUTPUT SPSCK OUTPUT MISO INPUT MOSI OUTPUT NOTE 4 5 5 1 4 BITS 6 1 LSB IN MASTER MSB OUT BITS 6 1 MASTER LSB OUT 10 11 10 7 6 ...

Page 382: ...K INPUT MISO INPUT MOSI OUTPUT 4 5 5 1 4 MSB IN BITS 6 1 8 6 10 5 11 NOTE SLAVE LSB OUT 9 3 LSB IN 2 7 BITS 6 1 MSB OUT Note Not defined but normally LSB of character previously transmitted SLAVE SS INPUT SPSCK INPUT SPSCK INPUT MISO OUTPUT MOSI INPUT 4 5 5 1 4 MSB IN BITS 6 1 8 6 10 NOTE SLAVE LSB OUT 9 3 LSB IN 2 7 BITS 6 1 MSB OUT 10 a SPI Slave Timing CPHA 0 b SPI Slave Timing CPHA 1 11 11 CPO...

Page 383: ...nly VCO Center of Range Frequency MHz fVRS 4 9152 32 0 4 5 to 5 5 V VDD only VCO Operating Frequency MHz fVCLK 4 9152 32 0 Characteristic Symbol Min Typ Max Unit Crystal load capacitance CL Consult crystal manufacturer s data Crystal fixed capacitance C1 2 CL Consult crystal manufacturer s data Crystal tuning capacitance C2 2 CL Consult crystal manufacturer s data Feedback bias resistor RB 22MΩ Se...

Page 384: ...tAL Tracking mode entry frequency tolerance DTRK 0 3 6 Acquisition mode entry frequency tolerance DUNT 6 3 7 2 LOCK entry freq tolerance DLOCK 0 0 9 LOCK exit freq tolerance DUNL 0 9 1 8 Reference cycles per Acquisition mode measurement nACQ 32 Reference cycles per Tracking mode measurement nTRK 128 Automatic mode time to stable tACQ nACQ fXCLK 8 VDDA fXCLK KACQ If CF Chosen Correctly Automatic st...

Page 385: ...d time mass erase tnvhl 100 µs FLASH program hold time tpgs 5 µs FLASH program time tPROG 30 40 µs FLASH return to read time trcv 4 4 trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing HVEN to logic 0 1 µs FLASH cumulative program hv period tHV 5 5 tHV is defined as the cumulative high voltage programming time to the same ro...

Page 386: ...Electrical Specifications Technical Data MC68HC908AB32 Rev 1 0 386 Electrical Specifications MOTOROLA ...

Page 387: ...uction This section gives the dimensions for 64 pin plastic quad flat pack case 840B 01 Figure 24 1 shows the latest package drawing at the time of this publication To make sure that you have the latest package specifications contact one of the following Local Motorola Sales Office World Wide Web at http www motorola com semiconductors Follow the World Wide Web on line instructions to retrieve the...

Page 388: ...37 L 12 00 REF 0 472 REF M 5 10 5 10 N 0 13 0 17 0 005 0 007 P 0 40 BSC 0 016 BSC Q 0 7 0 7 R 0 13 0 30 0 005 0 012 S 16 95 17 45 0 667 0 687 T 0 13 0 005 U 0 0 V 16 95 17 45 0 667 0 687 W 0 35 0 45 0 014 0 018 X 1 6 REF 0 063 REF NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD...

Page 389: ... 3 MC Order Numbers 389 25 2 Introduction This section contains ordering numbers for the MC68HC908AB32 25 3 MC Order Numbers Table 25 1 MC Order Numbers MC order number 1 Notes 1 FU Quad Flat Pack C Operating temperature range 40 C to 85 C M Operating temperature range 40 C to 125 C Operating temperature range MC68HC908AB32CFU 40 C to 85 C MC68HC908AB32MFU 40 C to 125 C ...

Page 390: ...Ordering Information Technical Data MC68HC908AB32 Rev 1 0 390 Ordering Information MOTOROLA ...

Page 391: ......

Page 392: ...f the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of direc...

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