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Summary of Contents for MC68824

Page 1: ......

Page 2: ...mmands II Buffer Structures II Signals II Bus Operation II TBC Interfaces II Electrical Specifications II Ordering Information and Mechanical Data II IEEE 802 4 Operation II Frame Formats and Addressing II Bridging II Performance ...

Page 3: ... liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent right nor the rights of others Motorola Inc general policy does not recommend the use of its components in life support applications wherein a failure or malfunction of the component may directly threaten life or injury Per Motorola Terms and Conditions of...

Page 4: ...rame Reception Overview 1 6 Frame Transmission Overview 1 7 Section 2 Tables TBC Private Area 2 1 Next Station Address 2 1 Previous Station Address 2 3 Hi Priority Token Hold Time 2 3 Last Token Rotation Time 2 3 Token Rotation Time at Start of Access Classes 2 4 Target Token Rotation Time for Access Classes 2 4 Token Rotation Time at Start of Ring Maintenance 2 4 Target Rotation Time for Ring Mai...

Page 5: ...set PTP 2 13 Initial In Ring Desired 2 13 Initial Address Length 2 13 Response Destination Address Pointer 2 13 Response Pointer 2 13 Request with Response Pointer 2 14 Command Parameter Area 2 14 Interrupt Status Words 2 15 Interrupt Status Word 0 2 15 Interrupt Status Word 1 2 17 Interrupt Masks 2 19 Statistics 2 19 Number of Tokens Passed 2 20 Number of Tokens Heard 2 20 Number of Passes Throug...

Page 6: ...lue 3 13 Command Parameter Area 3 13 READ VALUE Command 3 16 SET VALUE Command 3 16 Buffer Descriptor Function Code 3 17 Frame Descriptor Function Code 3 17 Data Buffers Function Code 3 17 Set Pad Timer Preset Register PTP 3 17 Set One Word 3 18 Set Two Words 3 18 Testing 3 18 SET INTERNAUEXTERNAL LOOPBACK MODE Command 3 19 HOST INTERFACE TEST Command 3 19 FULL DUPLEX LOOPBACK TEST Command 3 20 TR...

Page 7: ...a Frame 4 8 Initialization Performed by Host 4 9 Management of Transmission Queues 4 9 Examples of TBC Transmission Queues 4 10 Adding a Frame to a Transmission Queue 4 11 TBC s Actions Upon Transmission 4 11 Reception of Frames 4 12 Initialization Performed by Host 4 12 Reception Queues and Free Pools 4 13 TBC s Action Upon Reception 4 14 Request with Response RWR Transmission 4 15 Reception of R...

Page 8: ...ement Mode 5 8 Signal Summary 5 9 Section 6 Bus Operation 6 1 Host Processor Operation Mode 6 1 6 1 1 Host Processor Read Cycles 6 1 6 1 2 Host Processor Write Cycles 6 1 6 1 3 Interrupt Acknowledge Cycles 6 2 6 2 DMA Operation 6 3 6 2 1 DMA Burst Control 6 3 6 2 2 TBC Read Cycles 6 4 6 2 3 TBC Write Cycles 6 4 6 3 Bus Exception Control Functions 6 4 6 3 1 Normal Termination 6 6 6 3 2 Halt 6 6 6 3...

Page 9: ... and Mechanical Data 9 1 Package Types 9 1 9 2 Standard Ordering Information 9 1 9 3 Pin Assignments 9 2 9 4 Package Dimensions 9 3 Appendix A IEEE 802 4 Operation A 1 Functions A 1 A 2 Steady Station Operation A 1 A 3 Initialization A 2 A 4 Passing the Token A 2 A 5 Adding New Stations A 3 A 6 Priority A 4 Appendix B Frame Formats and Addressing 8 1 Frame Formats and Addressing 8 1 8 1 1 Preamble...

Page 10: ...sing B 4 Group Addressing B 6 Promiscuous Listener B 6 Appendix C Bridging Interconnection of Networks C 1 Hierarchical Addressed Bridging C 1 Hierarchical Addressed Bridging Implementation C 2 Lower Bridges C 3 Flat Addressed Bridging Overview C 3 Source Routing Implementation C 4 Route Designators C 5 Source Routing Operation C 6 Appendix 0 Performance MC68824 USER S MANUAL MOTOROLA ...

Page 11: ... 5 4 Request Channel Encodings for MAC Mode SMREQ 1 5 6 5 5 Request Channel Encodings for Station Management Mode SMREQ O 5 7 5 6 Indication Channel Encodings for MAC Mode SMIND 1 5 7 5 7 Encodings for Station Management Mode SMIND O 5 8 5 8 Typical Station Management Sequence 5 8 6 1 Host Processor Read Cycle with Two Wait States 6 2 6 2 Host Processor Write Cycle 6 2 6 3 Interrupt Acknowledge Cy...

Page 12: ...rocessor Write Cycle 8 6 8 3 Interrupt Acknowledge Cycle 8 6 8 4 Bus Arbitration 8 7 8 5 Read Cycle and Slow Read Cycle 8 8 8 6 Write Cycle 8 9 8 7 TBC Read Cycle with RETRy 8 10 8 8 Read Cycle with Bus Error 8 11 8 9 BR After Previous Exception 8 12 8 10 Short Exception Cycle 8 12 8 11 Clock ClK 8 13 8 12 TBC Serial Data RXD and TXD and Serial Clocks RClK and TClK 8 13 MC68824 USER S MANUAL MOTOR...

Page 13: ...gister Format 3 3 3 5 Interrupt Vector 3 4 3 6 Read Value Opcodes 3 14 3 7 Set Value Opcodes 3 15 3 8 Test Buffer Format 3 20 3 9 Test Buffer for Returned Data 3 21 5 1 Bus Exception Conditions 5 2 5 2 Signal Summary 5 9 6 1 Bit Bus Access CS O and R w O 6 12 6 2 16 Bit Bus Access CS O and R w O 6 12 MOTOROLA xii MC68824 USER S MANUAL ...

Page 14: ...microprocessor interface re quired A microcoded fully linked buffer management scheme queues frames during transmission and reception and optimizes memory use This VLSI implementation significantly reduces the cost of a MAP network 1 1 FEATURES The MC68824 provides the following Low Power Consumption through 2 Micron HCMOS Fabrication MAC Options Suitable for Real Time Environments Four Receive an...

Page 15: ... factory local area network through the Manu facturing Automation Protocol MAP specification based on the 150 051 reference model 1 2 1 150 051 Reference Model The industry accepted communications model is the Inter national Standards Organization ISO reference model of Open Systems Interconnection 051 The model specifies seven layers with each layer responsible for providing spe cific services to...

Page 16: ...terworking 802 1 broadband advisory 802 7 and fiber optic advisory 802 8 802 1 MANAGEMENT 802 2 LLC I BBBBB Figure 1 2 IEEE Standard Model 1 3 IEEE 802 4 TOKEN BUS LOCAL AREA NETWORKS DATA LLC LINK LAYER MAC PHYSICAL LAYER The following paragraphs briefly describe the token bus operation and the options outlined in the IEEE 802 4 standard 1 3 1 Token Bus Operation The IEEE 802 4 token passing bus ...

Page 17: ... do not have much data to transmit do not add unnecessary delay to the token rotation time The longer the token rotation time is the longer it is between each station s opportunity to transmit Not being a part of the logical ring allows these stations to have less functionality simpler software and lower cost Whenever a station needs data from a station that is not a member of the logical ring the...

Page 18: ...st channel is from the TBC to the modem and consists of TXCLK supplied by the modem TXSYMO TXSYM1 TXSYM2 and SMREQ The indication channel is from the modem to the TBC and consists of RXCLK supplied by the modem RXSYMO RXSYM1 RXSYM2 and SMIND Both the TBC and the modem can request station management mode The TBC requests station management mode in order to give commands and the modem requests stati...

Page 19: ...scriptors contain an offset value set by the user which tells how far from the beginning of the data buffer the actual data begins The offset feature can be used to add or subtract upper layer headers making it unnecessary to recopy data Data buffers contain only data and are flexible in size 1 8 OVERVIEW OF TBC FUNCTIONAL OPERATION The following paragraphs provide a high level summary of the comm...

Page 20: ...tten into shared memory an indication of its reception and its status are written into the frame descriptor 1 8 3 FRAME TRANSMISSION OVERVIEW Data frames are transmitted from one of four transmission priority queues Frames are only transmitted out of the enabled priority queues On reception of the token by the station the TBC checks the transmission queues for frames to be sent If frames are prese...

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Page 22: ...Command for details After initialization the TBC keeps an on chip pointer to this private area The private area should never be directly accessed by the host as this would not guarantee IEEE 802 4 operation The parameters in the private area should only be set and read by the SET READ VALUE commands through the command parameter area see 3 5 SET READ VALUE The format of the TBC private area is sho...

Page 23: ...ROUTING MALINTEILSOLlCIT_COUNT 802 4 RX FRAME STATUS ERROR MASK TX QUEUE ACCESS CLASS 6 STATUS TX QUEUE ACCESS CLASS 6 HEAD OF QUEUE POINTER ZERO TX QUEUE ACCESS CLASS 4 STATUS TX QUEUE ACCESS CLASS 4 HEAD OF QUEUE POINTER ZERO TX QUEUE ACCESS CLASS 2 STATUS TX QUEUE ACCESS CLASS 2 HEAD OF QUEUE POINTER ZERO ZERO TX QUEUE ACCESS CLASS 0 STATUS TX QUEUE ACCESS CLASS 0 HEAD OF QUEUE POINTER ZERO RX ...

Page 24: ...en The IEEE 802 4 standard specifies the maximum value for this timer to be 216 1 octet times which therefore requires the user to zero the upper three bits or the upper six bits of this word depending on the prescaling factor used However the TBC does not check that this parameter is within the specified range which allows the user to specify a timer with a maximum value of 222 1 This parameter m...

Page 25: ...ng maintenance These timers all run concurrently counting downward from an initial value to zero at which point their status is expired When the station begins processing the token at a given access class the associated internal token rotation timer is reloaded with the value of the target token rotation time for that access class When the station receives the token again it may send data from tha...

Page 26: ...discussed in the APPENDIX C BRIDGING Offset 20 o C B A Source Routing Target ID 2 1 12 Segment Number Mask for Source Routing The segment number mask determines which part of the routing designator is the segment number and which part is the bridge number See APPENDIX C BRIDING for details Offset 22 o c 2 1 13 MalLlnter_SoliciLCount B A 4 Segment Number Mask for Source Routing Ma lnteLSoliciLCount...

Page 27: ... status word to zero indicating that the queue is enabled and full When the TBC is finished transmitting from the queue it sets the queue empty bit to one A transmit queue except for class 6 frames must be enabled at least one token rotation time before it can contain data or before the station enters the logical ring This is done so the token rotation timers for each access class have a valid val...

Page 28: ...or Pointer LSB The free buffer descriptor pointer is a 32 bit pointer containing the address of the first free buffer descriptor in the linked list of the free buffer descriptor pool The TBC uses these free buffer descriptors upon reception of a frame This pointer is initialized by the host through the initiali zation table and may be altered or read via the SET READ VALUE command thereafter For m...

Page 29: ...t through the initialization table and may be altered or read via the SET READ VALUE command thereafter The middle and high words should be zero if the address length is 16 bits Note that the individual address mask is stored following the IEEE format Offset 66 68 6A D e B A Individual Address Mask low Word Individual Address Mask Middle Word Individual Address Mask High Word lSB I 2 1 22 Non RWR ...

Page 30: ...f time from the receipt of the end delimiter at the receiving station s physical medium interface until the impression of the first bit of the preamble on the physical medium by the receiving station s transmittter The safety margin in the time interval is no less than one MAC symbol time MAC symbols are defined as the smallest unit of information exchanged between the MAC sublayer entities MAC sy...

Page 31: ...e TBC to pass status statistic counters and command return information parameters to the host The format of the initialization table is shown in Figure 2 3 2 2 1 Private Area Function Code Bits 0 3 of the initialization table word 0 contain the function code values that may be required by the system to access the private area If no function codes are used this word does not need to be initialized ...

Page 32: ...SS 2 STATUS Host 3A INITIAL TX QUEUE ACCESS CLASS 2 HOQ POINTER Host 3E ZERO Host 40 INITIAL TX QUEUE ACCESS CLASS 0 STATUS Host 42 INITIAL TX QUEUE ACCESS CLASS 0 HOQ POINTER Host 46 ZERO Host 48 INITIAL RX QUEUE ACCESS CLASS 6 EOQ POINTER Host 4C INITIAL RX QUEUE ACCESS CLASS 4 EOQ POINTER Host 50 INITIAL RX QUEUE ACCESS CLASS 2 EOQ POINTER Host 54 INITIAL RX QUEUE ACCESS CLASS 0 EOQ POINTER Hos...

Page 33: ... TBG NUMBER OF TOKENS HEARD THRESHOLD Host NUMBER OF TOKENS HEARD TBG NUMBER OF NO_SUGGESSOR 8 ARGS THRESHOLD Host NUMBER OF NO SUGGESSOR 8 ARCS TBG NUMBER OF WHOJOLLOWS TRANSMITIED THRESHOLD Host NUMBER OF WHOJOLLOWS TRANSMITIED TBG NUMBER OF TOKEN PASSES THAT FAILED THRESHOLD Host NUMBER OF TOKEN PASSED THAT FAILED TBG NUMBER OF NON_SILENCE THRESHOLD Host NUMBER OF NON_SILENCE TBG NUMBER OF FCS ...

Page 34: ... modified using the SET CLEAR IN_RING DESIRED command Offset D C B A 7A IR I A L o l o o l o o l o l o I I o o I o I o 2 2 6 Initial Address Length The initial address length is a Boolean located in bit 14 A one indicates a 48 bit address and a zero indicates a 16 bit address Note that the MAP specification specifies 48 bit addresses only Offset D C B A 7A 1R I A L O I o o l o o l o l o o 1 o l o ...

Page 35: ...WO WORDS and READ VALUE commands For these commands the command area is a three word area with the first word containing the parameter opcode to be set or read The other two words contain the new parameter when setting the value of that parameter For a description of the parameter opcodes see Tables 3 7 and 3 8 The format of the command parameter area when using other commands is defined in the sp...

Page 36: ...F IRXRWR ITXDF ITXRDF ITXRWR IUNR lOVER IBDPL IFDPL IBAERRI TP ITSK ITXQE IBDPE IFDPE ITCC I TCC TBC Command Complete This bit is set upon completion of execution of all commands except RESET LOAD INITIAL IZATION TABLE FC and CLEAR INTERRUPT STATUS FDPE Frame Descriptor Pool Empty This bit is set after the last frame descriptor FD in the free frame descriptor pool is used and linked to one of the ...

Page 37: ...or The host has given the TBC new pools of free FDs and free BDs The host has enabled the TBC to resume transmitting by issuing the START or RESTART command if the TBC has more to transmit If a second bus address error occurs before the host has dealt with the first one i e the appropriate CLEAR INTERRUPT STATUS command was not given then the TBC enters an endless loop of severe interrupts and wai...

Page 38: ...FCS error overrun lack of BDs this bit will not be set even if the frame is accepted and linked to the appropriate receive queue If such a frame is accepted the RX data frame bit will be set although the frame control is that of a RWR frame RXDF Received Data Frame This bit is set when the TBC accepts a non RWR data frame or an invalid request with response frame after the confirmation word has be...

Page 39: ...NEXF10 Unexpected Frame 10 The TBC sets this bit when it executes the unexpected frame 10 transition in the IEEE 802 4 access control machine ACM It occurs when the TBC attempted to solicit a new successor and while waiting for a response heard either a data frame not sent by itself a set successor frame not addressed to it or another type of control frame not sent by itself When this event occurs...

Page 40: ...tected that the TBC has transmitted for more than a half second If an intelligent modem is used then more information can be obtained via the physical command Upon detecting this event the TBC sets this bit and goes to OFFLINE 2 2 12 Interrupt Masks Interrupt masks have the same format as interrupt status words If an interrupt status condition event occurs and the interrupt status bit is not alrea...

Page 41: ...e disabled using the SET MODE 1 command 2 2 13 3 NUMBER OF PASSES THROUGH NO SUCCESSOR 8 This statistic indicates the number of times this station has gone through the no successor 8 arc in the state machine This happens when the TBC fails to pass the token and does not succeed in finding a new successor station The counter is incremented only if the TBC thinks it is not the only active station in...

Page 42: ...he E bit reset 2 2 14 3 E BIT ERRORS E bit errors count the number of received frames with the E bit set in the end delimiter The E bit or error bit is set by the regenerative repeater headend remodulator when the headend detects a FCS error on the forward channel If this error occurs frames may be accepted if the appropriate bit is set in the receive frame status error mask see 4 1 1 2 RECEIVE ST...

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Page 44: ...t status word 0 which if enabled can generate an interrupt to the host The TBC command set is divided into the following cate gories Initialization Set Operation Mode TX Data Frames Set Read Value Test Notify TBC and Modem Control Table 3 1 shows the commands for each category while Table 3 2 illustrates each command s encodings Table 3 1 TBC Commands by Categories INITIALIZATION TEST LOAD INITIAL...

Page 45: ... 83 0 1 0 0 84 0 1 0 1 85 0 1 1 0 86 0 1 1 1 87 1 0 0 0 88 0 0 0 0 90 0 Y Y Y A1 A7 1 0 0 0 A8 0 0 0 0 80 0 1 Y 0 B4 B6 1 0 0 0 88 1 1 0 0 BC Y 1 0 0 C4 CC 0 1 0 1 C5 0 1 1 0 C6 0 1 1 1 C7 1 Y 1 1 CB CF 0 0 0 Y DO D1 0 0 0 0 EO 0 0 0 0 FO 1 0 0 0 F8 1 1 1 1 FF Commands are executed by the TBC either while uninitialized in the OFFLINE or IDLE modes or in the use_token state in between transmitting ...

Page 46: ...ister during DMA transfers See 6 2 DMA OPERATION for details on DMA transfers The format of the 32 bit data register is shown in Table 3 4 Table 3 4 Data Register Format 31 24 23 16 15 8 7 a OR3 I OR2 I OR1 ORO 3 1 4 Interrupt Vector Register IV The 8 bit interrupt vector register is used to store the 8 bit interrupt vector returned to the host by the TBC for the interrupt acknowledge lACK cycle T...

Page 47: ...he TBC and to change the access control machine ACM state from OFFLINE to IDLE The following routine is used to initialize the TBC by the host processor For every command except the RESET and LOAD INITIALIZATION TABLE FUNCTION CODE commands the done bit in the status word of the command parameter area may be checked to ensure the instruction was executed by the TBC if the host processor has cleare...

Page 48: ... internal resources upon execution of this command The TBC will return confirmation of this command in the CPA offset 9C of the initialization table provided this word was cleared prior to command execution If no errors are detected during the self test a value of one will be returned in the status word of the CPA Otherwise a value of 0011 hex will be stored in the status word of the CPA If a bus ...

Page 49: ...he IDLE command causes the TBC to Clear any_send_pending 802 4 boolean Reset the receive and transmit machines Enable the receive machine Set noise expected see 2 2 13 STATISTICS Zero the lasLtoken_rotation_timer TRT variable located in the private area Zero the internal token_rotation_timer TRT counter Set the no_successor status bit Zero the transmitter fault count located in the private area Lo...

Page 50: ... this subsection This command is normally given only as part of an initialization sequence or during testing 4 3 2 1 0 o I 0 I 1 I 0 ICUFC ICACF IlSTT IPDRF CUFC Recognize Frames with Undefined Frame Control not part of IEEE 802 4 1 Recognize frames with undefined frame control as valid data frames o Do not recognize frames with undefined frame control as valid data frames When disabled frames wit...

Page 51: ...t processor that a RWR frame has been received and waits for the host processor to prepare a response and issue a RESPONSE READY command See 4 4 REQUEST WITH RESPONSE RWR TRANSMISSION and 4 5 RECEPTION OF RWR FRAMES AND TRANS MISSION OF RESPONSE for a complete description of RWR frames 3 3 2 SET MODE 2 Command The default setting is zero for all modes described in this subsection This command is n...

Page 52: ...ring a data frame with SA not equal to TS which could cause the TBC to incorrectly believe that another station is transmitting In this mode the TBC will wait ap proximately one slot time before transmitting a solicit successor or token frame after trans mitting a data frame or before transmitting a non retry request with response data frame RSR Recognize Source Routing 1 Recognize source routing ...

Page 53: ... standard all frames are transmitted with the standard 32 bit frame check sequence FCS and the FCS or CRCis checked for correctness in all received frames Received frames with CRC errors are treated as noise bursts by the access control machine ACM This mode applies to all data frames i e there is not a separate indication for each frame The TBC always generates and attaches the CRC for all contro...

Page 54: ...arameter Token rotation time at start of ring maintenance Statistic Target token rotation time for ring maintenance Parameter Ring maintenance timer initial value Parameter The prescaling mechanism provides a resolution of 8 or 64 octets for all the values listed above The amount of prescaling must be chosen such that after prescaling the parameters will fit into 15 bits Thus if the largest target...

Page 55: ...smit queues The RESTART command is used after transmission of data frames was suspended by an earlier STOP command If the TBC is not in_ring when this command is given the TBC will enter the logical ring if outstanding data frames remain to be transmitted The coding for this command is C6 and its format is shown below 1 I 1 I 0 o I 0 I 1 I 1 I 0 3 4 3 START Command This command is used by the host...

Page 56: ...ial ization table to transfer parameters between the host and the TBC 3 5 1 Command Parameter Area The command parameter area CPA is a seven word memory area within the initialization table offset 90 to 9C used to set and read internal variables of the TBC which reside in the private area or on chip via the SET READ VALUE commands The CPA consists of the command area and the command result area Th...

Page 57: ...at Start of Access Class 0 802 4 Target Rotation Time Access Class 0 802 4 TRT at Start of Ring Maintenance 802 4 Target Rotation Time Ring Maintenance 802 4 Ring Maintenance Timer Initial Value 802 4 Bridge Pair Source Segment Number Bridge Pair Target Segment Number Source Routing User Mask Maximum_lnter_SoliciLCount 802 4 RX Frame Status Error Mask Status of TX Queue 6 Tx Queue Access Class 6 H...

Page 58: ...Address Mask Low Word 62 4 GA MASK MED_HI Group Address Mask Medium and High Words 66 2 lA MASK LOW Individual Address Mask Low Word 68 4 IA MASK MED_HI Individual Address Mask Medium and High Words 6C 2 MAX RETRY Non RWR Maximum Retry Limit 802 4 6E 2 RWILMAX RETRY RWR Maximum Retry Limit 802 4 NOTE 1 This value is not meaningful if the address length is 16 bits The command result area is the fou...

Page 59: ... specified via the SET MODE 3 command 3 The boolean nexLstation_known is returned in CPA RESULT bit 15 if the host has requested the next station address opcode 00 If next station known is true this bit is zero and the next station address that is returned is valid if false this bit is one and the next station value that is read is not meaningful The code for the READ VALUE command is 90 and its f...

Page 60: ...ng The coding is 87 and the format is shown below 7 6 4 1 1 0 o 1 1 1 1 3 5 3 4 SET PAD TIMER PRESET REGISTER PTP The pad timer preset register is used by the TBC to set the length and pattern of the preamble and the minimum number of preamble octets transmitted between frames The initial value of this register is loaded by the host at offset 78 of the initialization table After initialization thi...

Page 61: ...ONE WORD command into the command register The opcodes for the SET ONE WORDITWO WORDS commands are listed in Table 3 7 The co ing for this command is 86 and its format is shown below 1 I 0 I 0 o I 0 I 1 I 1 I 0 3 5 3 6 SET TWO WORDS The SET TWO WORDS command is used to set four byte TBC param eters which reside in the private area The host must load the opcode into CPA VALO and the new parameter v...

Page 62: ...nternal loopback mode of operation This command controls the internal loopback from TXSYMO TXSYM1 and TXSYM2 to RXSYMO RXSYM1 and RXSYM2 respectively In internal loopback mode transmitted in formation is looped back as received information internally to the chip Also in internal loopback mode the external transmit output pins send silence symbols regardless of the symbols being generated internall...

Page 63: ...or Register Load the Function Code of the init table pointer into DRO Issue LOAD INITIALIZATION TABLE FC Command Wait until Semaphore Register is FF Load the Init Table Pointer into DR Issue INITIALIZE Command Issue SET MODE 3 Command to set SWAP and HLEN Bits Prepare First 34 Bytes of Test Buffer Load CPA VALO with Function Code of Buffer if Needed Load CPA VAL1 and CPA VAL2 with Pointer to Buffe...

Page 64: ...ted by the TBC Note that the indication bytes do not contain sufficient information to determine whether the test was a success or failure The data itself must be checked by the host The following routine may be used to run the full duplex loopback test Prepare the Initialization Table Issue RESET Command Wait until Semaphore Register is FF Initialize the Interrupt Vector Register Load the Functio...

Page 65: ...atus word 0 TXQE the test should be ended by issuing the OFFLINE command Command confirmation and status are returned to the command return area in the initialization table The OFFLINE command must be given before the token hold timer expires while running in external loopback mode To check the tests results the host can check the FD confirmation word for TX queue access class 6 If detected CRC un...

Page 66: ...ister has a different format in this test than in normal mode as shown PTP register format for the receive test DeB A 3 p I p I p Where m Frame s length number of bytes between the start delimiter up to but not including the CRC FCS minus two 2 b Number of preamble octets between frames minus one 1 p Pattern of preamble octet The command confirmation bit is set by the TBC upon completion of the OF...

Page 67: ...sue RECEIVER TEST Code is BO Wait for Command Confirmation which Indicates Acceptance of the Test Wait until FD or BD Pool Empty Bits 1 and 2 in Interrupt Status Word 0 Issue the OFFLINE Command Check for Received Frames Status in the FD Class 6 NOTE In order to check for command completion the host must clear the done bit in CPA status word before issuing a command to the TBC 3 6 6 Sequence for R...

Page 68: ...nitialize Modem if in External Loopback Mode Clear Done Bit in CPA Status Word Issue FULL DUPLEX LOOPBACK MODE TEST Code is B8 Wait for Done Bit in Status Word Read Indication 0 and 1 for Errors Compare Returned Data to Data which was given to the TBC TRANSMITIER TEST Issue SET MODE 3 Command to set SWAP HLEN PS3 and TCDS Bits if Needed Prepare Access Class 6 TX Queue Issue SET ONE WORD Command to...

Page 69: ...d Frames Status in the FD Class 6 NOTE In order to check for command completion the host must clear the done bit in CPA status word before issuing a command to the TBC 3 7 NOTIFY TBC The two commands in this category are used to notify the TBC that a response frame is ready when using the non predefined RWR mechanism or to clear some interrupt status bits 3 7 1 CLEAR INTERRUPT STATUS Command This ...

Page 70: ...de see 4 5 RECEPTION OF RWR FRAMES AND TRANSMISSION OF RESPONSE for a description of this mechanism The coding for this command is C5 and its format is shown below 1 I 1 I 0 I 0 I 0 I 1 I 0 I 1 3 8 MODEM CONTROL Two commands are provided to allow the TBC to communicate management services to the physical layer of the network 3 8 1 PHYSICAL Command This command is used by the host processor to cont...

Page 71: ...There are two main types of commands which can be issued by the host to the physical layer immediate and data transfer Immediate commands do not involve data exchange with the modem but rather provide a simple interface to allow the host to control the modem through the TBC Data transfer commands are designed for intelligent modems which need additional information to be transferred between the ho...

Page 72: ...SFER COMMANDS Data transfer commands are designed for intelligent mo dems which need more information The serial station management data interface provides a sophisticated way for the host to communicate with the modem through the TBC Upon receiving this type of command the TBC will go through the steps described below 1 It is assumed that the TBC and the modem are in MAC mode or that a modem erro...

Page 73: ...oint the TBC is in SM idle mode with TXSYM2 0 TXSYM1 0 TXSYMO 1 and SMREQ O The modem is in the idle state with RXSYM2 0 RXSYM1 0 and SMIND O 13 The TBC is ready to accept another command 3 S 2 END PHYSICAL Command This command causes the TBC to exit from station management mode Upon receiving the command the TBC sets SMREQ 1 and waits for the modem to set SMIND 1 before setting the command done b...

Page 74: ... or disabled using the SET ONE WORD command The TBC confirms transmission of the frames in each frame descriptor as they are sent out During reception the TBC reverses the process to use frame descriptors and buffer descriptors from the pre linked free frame descriptors pool and free buffer descriptors pool as frames are received assigning these frames to the proper reception queue Receive queues ...

Page 75: ... through the seven layers ofthe ISO OSI structure Address and control information can then be appended to and removed from the front of each frame as it passes through the software layers during transmission and reception respectively The TBC can access the first data buffer on an odd byte boundary while transmitting further removing restrictions on building frames 4 1 BUFFER STRUCTURES The follow...

Page 76: ...TION ADDRESS BYTE 5 22 MAC SOURCE ADDRESS BYTE a 23 MAC SOURCE ADDRESS BYTE 1 IEEE LSB 24 MAC SOURCE ADDRESS BYTE 2 25 MAC SOURCE ADDRESS BYTE 3 26 MAC SOURCE ADDRESS BYTE 4 27 MAC SOURCE ADDRESS BYTE 5 28 RESERVED 2A RESERVED Figure 4 3 Frame Descriptor Format 4 1 1 1 FD CONFIRMATION INDICATION WORD FORMAT The first word of the frame descriptor contains the frame descriptor confirmation indicatio...

Page 77: ...nse o No meaning 1 If NIP 1 then no response was received to an RWR frame If NIP 0 then response was received on one of the following retries UF Unexpected Frame o No meaning 1 Unexpected frame received during RWR RD RTO Number of Tries Number of tries except if the MAX RETRY LIMIT was reached then it is the number of retries Refer to 4 4 REQUEST WITH RESPONSE RWR TRANSMISSION and 4 5 RECEPTION OF...

Page 78: ...ed the data is copied to the data buffer s in its entirety The frame data length reflects the number of bytes copied to the data buffer s If not enough buffers are available in the free buffer pool the TBC receives the frame s header information as long as free FDs are available The correct frame length is stored in the FD o c B A Reserved CRCE EBIT FOVF NOISE FTL NOBUF CRC error occurred in the f...

Page 79: ...sponsible for updating this field while in the receive case the TBC is Three frame categories are currently defined by IEEE 802 4 MAC control and LLC data Note that the host is forbidden from setting this byte to a MAC control value in the TX case See APPENDIX B FRAME FORMATS AND ADDRESSING for more details 4 1 1 9 MAC DESTINATION ADDRESS The MAC destination address can be either two or six bytes ...

Page 80: ...ppended to the front of the data and the offset may be changed for the next ISO layer so that the data does not have to be rewritten Note that bit Fof this word has a different meaning for the TX queue and the free buffer descriptor pool o C B A 2 iLABD iOF14 iOF13 iOF12 iOFll iOF10 i OF9 i OF8 i OF7 i OF6 iOF54 i OF4 i OF3 i OF2 i OFI OFO LABD Last Buffer Descriptor Transmit Queue Case TBC will u...

Page 81: ...is receive frame OL14 0LO Offset Length Number of unused data bytes in this buffer 4 1 2 5 NEXT BUFFER DESCRIPTOR POINTER This 32 bit address points to the next buffer de scriptor in the queue This pointer must be initialized by the host if the next BD is valid in both the transmit and free pool cases 4 1 3 Data Buffers A data buffer is a continuous block of memory reserved for message data Differ...

Page 82: ...he host has to decide how many are required for each frame Initialize the data buffer pointer offset 2 Set LABD last buffer descriptor bit located in the control and offset word offset 6 to one or zero depending on whether or not this is the last linked buffer for this frame Also the offset in bytes from the head of the data buffer to where actual data begins must be entered Load the data buffer l...

Page 83: ... s transmission 1 TBC completed this frame s transmission EMP Empty This bit resides in the confirmation indication word of the FD a This queue is not empty 1 This queue is empty EMP reflects the value of NPV as read by the TBC EMP is not valid if CFD abecause the host clears it when preparing the frame The CFD and EMP bits are set and cleared by the TBC in a single memory access after sampling NP...

Page 84: ... be issued to the TBC as in adding a frame to an empty queue A not sure queue that turns out to be an empty queue can be detected if there is a confirmed frame with the EMP bit in the confirmation word set and the NPV bit in the control word also set This event can be detected by an interrupt routine which could be run upon servicing a TBC interrupt triggered by the perceived end of the queue TXQE...

Page 85: ...e as well as the mechanism used by the TBC to do so 4 3 1 Initialization Performed by Host In order to allow the TBC to store the received frames the host must set up free frame descriptor and buffer descriptor pools as shown in the example of Figure 4 6 To enable the TBC to store incoming frames the host must prepare the following data structures 1 The free frame descriptor pool pointer located i...

Page 86: ...ointer offset OE if the next BD is valid i e LABD O 5 Memory space must be reserved for the data buffers pointed to by the BD s 4 3 2 Reception Queues and Free Pools Four queues are maintained for received frames one for each priority class Note that these queues may not be disabled by the host At initialization time the host must set the RX EOO pointer for each access class These pointers may be ...

Page 87: ... Therefore the host must not remove the last FO which serves as the dummy FD from the queue In Figure 4 8 the TBC has received one frame and has stored it using F02 and two BOs B02 and B03 4 3 3 TBe s Actions Upon Reception As the TBC accepts frames addressed to it it takes frame descriptors and buffer descriptors from the beginning of the free frame descriptor and free buffer descriptor pools MOT...

Page 88: ...ast BD for this frame and the number of unused data bytes in this buffer 3 The TBC will load the data from the frame into the data buffer s associated to the BD s which was were pulled from the free pool 4 The TBC will check the private area to find the last FD residing in the appropriate receive queue It will change this last FD s next receive valid NRV bit to a one indicating that there is at le...

Page 89: ...SION OF RESPONSE Upon receiving an RWR frame addressed to this station the TBC will store it into the appropriate receive queue and perform the following steps The source address of the received frame is stored into the destination address field of the FD pointed to by the response destination address pointer This pointer resides in the ini tialization table at offset 84 and must have been previou...

Page 90: ...me value as the response pointer offset 88 The TBC will set DA equal to SA of received frame in the FD pointed to by the response destination address pointer offset 84 Case 2 The TBC is in predefined response mode and the DA of the response frame must be different from the SA of the received RWR frame The response destination address pointer offset 84 should have been previously set by the host to...

Page 91: ...sly In this case the RESPONSE READY command is executed only after complete reception of the RWR frame Thus the response is considered a valid response to the second request and will be transmitted This scenario also can take place if the response was ready to be transmitted but due to high load on the bus the TBC was not able to execute the RESPONSE READY command prior to receiving the second RWR...

Page 92: ...Input and output signals are functionally organized into the groups shown in Figure 5 1 Each of these groups is discussed in the following paragraphs 5 1 ADDRESS BUS A1 A31 This is a 32 bit when combined with UOS AO signal unidirectional with the exception of A1 and A2 which are bidirectional three state bus capable of addressing up to 4 gigabytes of memory A1 and A2 are used to address internal r...

Page 93: ...function code pins are not connected the user can ignore SET FUNCTION CODE commands see 3 5 3 Set Value 5 3 2 Bus Exception Conditions BECO BEC2 These input lines provide an encoded signal that indi cates an abnormal bus condition such as a bus error or reset The three bit bus exception control codes allow for eight different bus termination conditions BECD is the least significant bit and BEC2 is...

Page 94: ...ocessor when operating in slave mode In the master mode during any 16 bit bus cycle UOS is asserted if data is to be transferred over the data lines 08 015 and LOS is asserted if data is to be transferred over data lines 00 07 For an 8 bit bus configuration UOS functions as AO and LOS functions as data strobe AO is thus an extension of the lower address lines to provide the address of a byte in th...

Page 95: ...Bus Grant BG BG is an input that indicates to the TBC that bus control has been granted and that it may assume bus mastership as soon as the current bus cycle is completed The TBC will not take control of the bus until AS and BGACK are negated and the BEC pins are encoded as normal mode 5 4 3 Bus Grant Acknowledge BGACK BGACK is a bidirectional three state signal When BGACK is an asserted input si...

Page 96: ...nd for indicating data unit reception when in the MAC mode The interface also serves as a communication channel for passing station management requests indications and confirmations between the physical layer and the TBC Note that since the TBC is a half duplex part it will not hear its own transmission The following paragraphs describe the data request and data indication channel while Figure 5 3...

Page 97: ...for TXSYM2 TXSYM1 and TXSYMO are those shown in the Figure 5 4 When the TBC does not have any data to transmit it will encode ones on the TXSYM lines that is silence will be transmitted The TBC looks for silence on the RXSYM lines to determine if it can transmit Also note that the TBC does not receive its own transmission being a half duplex part SYMBOL TXSYM2 DATA ZERO 0 DATA ONE 0 PAD IDLE 0 NON...

Page 98: ...lled RXSYM3 in the 802 4G Draft Standard When in MAC mode the physical layer sends encoded indications of data unit reception silence non data bad signal data one and data zero The physical layer enters management mode SMIND O to send responses to management commands at the request of the TBC to report an error event at the initiative of the modem or to report real time data also at the initiative...

Page 99: ...O RXSYMI RXSYM2 RXSYMO MOTOROLA 5 8 STATE RXSYM2 RXSYMI RXSYMO ACK ACKNOWLEDGEMENT 0 1 NACK NON ACKNOWLEDGEMENT 1 0 IDLE 0 0 1 PHYSICAL LAYER ERROR 1 1 1 Where indicates RXSYMO contains the SM data when responding to a serial data command A 1 in that position indicates a serial SM data one or stop bit A 0 in that position indicates a serial SM data zero or start bit Figure 5 7 Encodings for Statio...

Page 100: ...1 ReadtWrite RiW Input Output High Low Three State1 Chip Select CS Input Low Data Transfer Acknowledge DTACK Input Output Low Three State1 Bus Request BR Output Low Open Drain2 Bus Grant BG Input Low Bus Grant Acknowledge BGACK Input Output Low Three State1 Receive Clock RXCLK Input Indication Channel SMIND Input Low Indication Channel RXSYMO Input Indication Channel RXSYM1 Input Indication Channe...

Page 101: ...II MOTOROLA 5 10 o l MC68824 USER S MANUAL ...

Page 102: ...8000 Family processor is the host processor with a clock signal identical to the TBe ClK 6 1 1 Host Processor Read Cycles Ouring the host processor read cycle the bus master asserts chip select CS read RIW and lower data strobe lOS OS The TBC then places data onto the data bus and asserts data transfer acknowledge OTACK to indicate to the bus master that the data is valid The semaphore register wi...

Page 103: ...ycle the host processor responds to an interrupt request from the TBC The timing of an interrupt acknowledge cycle is identical to an odd byte read cycle except that it is started by the assertion of the interrupt acknowledge lACK signal rather than chip select CS Note that chip select CS and interrupt acknowledge lACK are mutually exclusive signals and should not be asserted at the same time If i...

Page 104: ...er an a bit or a 16 bit bus configuration NOTE The TBC does not check for an odd pointer and does not generate an address error for an odd word boundary For an a bit data bus an odd pointer is proper For a 16 bit bus the TBC zeros the least significant address bit and therefore always presents an even word address to the bus The system designer must ensure that the TBC is not supplied with an odd ...

Page 105: ... controls the transfer of data to memory from the TBC internal registers or FIFO The functional timing for this operation is shown in Figure 6 5 The TBC drives FCO FC3 and A1 A31 pins with the address of the memory location to be written Then address strobe AS is asserted and depending on the data size upper data strobe UDS AO and lower data strobe LOS OS are asserted and RIW is driven low Data to...

Page 106: ...LOCK DELAY BEFORE TERMINATION NO FURTHER CYCLES UNTIL NO EXCEPTION RESERVEDI 7 L L L RESET RESET TBC REGISTERS AND LOGIC Figure 6 6 BEC Encoding Definitions bus cycle and wait for the BEC encoding to return to zero Each of the possible conditions is discussed in detail in the following paragraphs There are three possible cases for bus exceptions In the first case a very early bus exception occurs ...

Page 107: ...T OTACK ACTIVE AFTER HALT Figure 6 7 TBC Write Cycle with HALT 6 3 3 Bus Error When a logical two is encoded on the BEC pins the TBC aborts the current bus cycle and releases bus mastership After the BEC lines return to normal the TBC rearbitrates for the bus to report the bus error to the host processor by writing the address that caused the error into the DMA dump area in the initialization tabl...

Page 108: ...S9 EARLY ASYNCHRONOUS EXCEPTION LATE SYNCHRONOUS EXCEPTION Figure 6 8 TBC Read Cycle with Bus Error ClK INPUT BGACK SO SI S2 S3 S4 S5 S6 S7 S8 S9 SO SI S2 S3 S4 S5 S6 S7 OUTPUT ____________________________ Al A31 OUTPUT FCO FC3 OUTPUT AS r OUTPUT _______ 1 UDS lOS I OUTPUT R W I OUTPUT 00 015 INPUT oTACK 1 INPUT ________ RTY ON _ BECO BEC2 I INPUT 1 Figure 6 9 TBC Read Cycle with RETRY MC68824 USE...

Page 109: ...ven encoded on the BEC pins causes the TBC to execute an internal reset sequence Hardware and software reset will cause the TBC to execute the same steps see 3 2 5 RESET Command for more details 6 3 7 Undefined BEC Codes If a logical five or six is encoded on the BEC pins the TBC takes no action as shown in Figure 6 11 However the bus cycle may be extended one more clock cycle due to the debouncin...

Page 110: ... uses this M68000 bus arbitration protocol to request bus mastership before entering the DMA mode of operation The bus arbitration timing diagram is shown in Figure 6 12 OTHER BUS MASTER TBC CYCLE SO SI S2 S3 S4 S5 S6 S7 SO SI S2 S3 S4 S5 S6 S7 CLK INPUT Bii OUTPUT _ _ _ _ _ _ _ _ _ ______ INPUT _ _ _ _ _ _ _ _ _ _ _ 1 AS liD _ _ _ _ _ _ J BGACK 0 liD ___________ _ _ _ _ _ _ _ _ CLK INPUT NO BUS M...

Page 111: ...as long as the protocol is obeyed 6 4 3 Acknowledgement of Mastership Upon receiving a bus grant the TBC waits until AS and bus grant acknowledge BGACK are negated before asserting BGACK The negation of AS indicates that the previous master completed its cycle negation of BGACK indicates that the previous master has released control of the bus When these conditions are met the TBC asserts BGACK Af...

Page 112: ... required to switch bus masters must be known to predict system behavior For the TBC there are two types of overhead Time for the TBC to take control of the bus front end overhead and Time that occurs when the TBC releases control of the bus to another bus master back end overhead The timing diagram for the front end and back end overhead for the TBC is shown in Figure 6 14 6 5 1 Front End Overhea...

Page 113: ... bus master begins the next bus cycle 6 6 REGISTERS The following registers are user programmable the command register CR the data register DR and the interrupt vector register IV Table 6 1 shows how the TBC registers are accessed for 8 bit bus and Table 6 2 shows how the TBC registers are accessed using a 16 bit data bus Table 6 1 8 Bit Bus Access CS O and R W O A2 0 0 1 1 1 1 MOTOROLA 6 12 A1 0 ...

Page 114: ...is limited to data that is transmitted or received in the data buffers Initialization table entries and pointers and control data in frame descriptors MUST be organized to the Motorola standard Another consideration besides byte order is control line usage In case of the Intel 8086 Family the address lines always provide a full byte address using AO A signal called BHEN is used to indicate a data ...

Page 115: ...RRUPT FCO LOGIC FCI FC2 FCO FCI FC2 Al A2 A3 MMU FC3 II Al A31 1 1 AI A2 A3 A31 ADDRESS cs DECODE J AS AS AD SIZO DATA UDS STROBE SIZI GENERATION LOS os 00 031 16 00 015 R W R W DSACKO L r DSACKI DTACK RESET BUS BECO BERR EXCEPTIDN BECI HALT LOGIC BEC2 Figure 7 1 TBC to MC68020 Interface MOTOROLA MC68824 USER S MANUAL ...

Page 116: ... INTERFACE I BUS CONTROL ADDRESS BUS SERIAL AO INTERFACE Y 74LS373 I Y 74LS373 11 TXSYMO 2 RXSYMO 2 Al AI9 A20 A31 L V DTACK 7 ES CLOCK LOS BEC2 CLOCK 80186 UOS BECI EXCEPTION RESET TO R W BECO TBC lACK INTERFACE IRQ Bii 74LS245 I BGACK 74LS245 BG L DATA BUS 00 015 J l V DATA BUS TO MEMORY TBC Figure 7 2 TBe to iAPX 80186 Interface II ...

Page 117: ...ncoded requests for data transmission Physical Data Indication Channel In the MAC mode this channel is used by the physical layer to provide encoded indications of data unit reception to the TBC Physical Layer Management In the station management mode this interface also provides the ability to pass station management requests indications and confirmations between the MAC device and the phys ical ...

Page 118: ... voltage higher than max imum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either GNO or VOO The average chip junction temperature TJ in C can be obtained from where TA OJA Po PINT PliO TJ TA PO OJA Ambient Temperature C Package Thermal Resistance Junction to Ambient CIW PINT PI O 100 x VOO Wa...

Page 119: ...TXSYMO 2 which are measured from 2 5 V and 0 5 V High and low inputs are driven to 2 4 V and 0 5 V respectively for AC test purposes However input specifications are still measured from 2 0 V to O S V All specifications are valid under the following conditions VOO 4 75 V to 5 25 V VSS 0 V TA Tl to TH output load 130 pF and output current as specified in 8 4 OC ELECTRICAL CHARACTER ISTICS Num Chara...

Page 120: ... BGACK low 1 5 1 5 Assuming that BG is Active and BGACK and AS are Inactive for at least 2 ClK Periods 35 ClK on which AS is High to ClK on which BGACK 1 is High 36 ClK High to Address Valid 100 37 ClK High to Address FC High Impedance 70 38 ClK High to FC Valid 60 39 Address Valid to AS Valid 20 40 ClK High to AS UDS lDS low 50 41 ClK to AS UDS lDS High 55 42 AS High to Address FC Invalid 20 43 C...

Page 121: ... Fall Time see Note 8 68 ClK Width low see Note 8 69 RXClK TXClK Frequency 70 RXD Signals Setup Time 71 RXD Signals Hold Time 72 RXClK TXClK Rise Fall Time 73 RXClK TXClK Width low 74 RXClK TXClK Width High 75 RXClK TXClK Period 76 TXClK High to TXD Signals Output Delay Parts with an S suffix have the following characteristics 69 RXClK TXClK Frequency 73 RXClK TXClK Width low 74 RXClK TXClK Width ...

Page 122: ...timed from the earliest clock on which C5 and either data strobe are recognized during an MPU cycle Data 3 and OTACK will be timed from the earliest clock on which lACK and either data strobe during an lACK cycle 6 If CS or lACK is negated before UOS LDS the data bus will be three stated 4 pos before UOS LD5 negation 7 If an 8 bit bus is used only LOS need be considered If a 16 bit bus is used bot...

Page 123: ... OTACK OUTPUTI R W INPUTI Figure 8 2 Host Processor Write Cycle SO SI S2 S3 S4 S5 SW SW SW SW S6 S7 CLK INPUTI UOS LOS INPUTI lACK INPUTI 00 07 OUTPUTI O CK _ _ _________ ________ OUTPUTI R W INPUTI _ ____ IRQ OUTPUTI Jr _______________________________________ Figure 8 3 Interrupt Acknowledge Cycle MC68824 USER S MANUAL ...

Page 124: ...SO SI S2 S3 S4 S5 S6 S7 ClK INPUTl SA OUTPUTI I __ _t I__ l INPUTl AS 1 01 BGACK 1 01 __ TBC CYCLE NO BUS MASTER SO SI S2 S3 S4 S5 S6 S7 ClK INPUTl SA OUTPUTI IINPUTl AS I 11 01 BGACK OUTPUTI Figure 8 4 Bus Arbitration MC68824 USER S MANUAL II MOTOROLA ...

Page 125: ... OUTPUTI AS OUTPUTI UOS LOS OUTPUTI R W OUTPUTI 00 015 lNPUTI OTACK r I INPUTI NOTE The solid lines assume that the communication controller was bus master on the last cycle The dotted lines assume that there was a different bus master Figure 8 5 Read Cycle and Slow Read Cycle MOTOROLA MC68824 USER S MANUAL s u ...

Page 126: ...OUTPUTI UDS lOS OUTPUTI R W OUTPUTI 00 015 OUTPUTI DlACK INPUTI SO SI S2 S3 S4 S5 S6 S7 SO SI S2 S3 S4 S5 SW SW SW SW SW SW SW SW S6 S7 Figure 8 6 Write Cycle and Slow Write Cycle MC68824 USER S MANUAL II MOTOROLA 00 ...

Page 127: ... BECO BEC2 INPUTI CASE ONE If DTACK satisfies 1 then 48 and 58 are required If DTACK is active but does not satisfy 1 then 49 and 57 are required CASE TWO If DTACK is not active then 59 is required for the exception active set up time Parameter 61 is always required for the exception inactive set up time MOTOROLA R 1n Figure 8 7 TBC Read Cycle with RETRY MC68824 USER S MANUAL CASE ONE CASE TWO ...

Page 128: ...15 INPUT OTACK INPUTI BERR ON BECO BEC2 INPUT BGACK OUTPUTI SO SI S2 S3 S4 S5 SW SW S6 S7 EARLY ASYNCHRONOUS EXCEPTION OTACK INACTIVE SO SI S2 S3 S4 S5 SW SW S6 S7 1 1 lATE SYNCHRONOUS EXCEPTION OTACK ACTIVE Figure 8 8 Read Cycle with Bus Error MC68824 USER S MANUAL MOTOROLA L11 II ...

Page 129: ...ception CLK lNPUTI AS OUTPUTI EXCEPTION ON BECO BEC2 INPUT OTACK IINPUTI EXCEPTION ON BECO BEC2 INPUTI DTACK IINPUT BGACK OUTPUTI Figure 8 9 BR After Previous Exception SO SI S2 S3 S4 S5 SW SW S6 S7 CASE ONE CASE TWO NOTE Two alternatives of DTACK and exception Case one has DTACK occur after exception and case two has exception occur after DTACK Figure 8 10 Short Exception Cycle MC68824 USER S MAN...

Page 130: ...T TXD 1 Figure 8 11 Clock ClK 1 _ _ _ I OUTPUT _______J RXD SIGNALS SMIND RXSYM2 RXSYMl RXSYMO TXD SIGNALS SMREQ TXSYM2 TXSYMl TXSYMO Figure 8 12 TSC Serial Data RXD and TXD and Serial Clocks RClK and TClK MC68824 USER S MANUAL MOTOROLA S L1 l II ...

Page 131: ...II MOTOROLA 8 14 MC68824 USER S MANUAL ...

Page 132: ...y Range Pin Grid Array 1 MHz to 10 MHz 10 0 MHz O C to 70 C RC Suffix 1 MHz to 12 5 MHz 12 5 MHz O C to 70 C 5 MHz to 16 67 MHz 16 67 MHz O C to 70 C 10 kHz to 10 MHz 10 MHz O C to 70 C 10 kHz to 12 5 MHz 12 5 MHz O C to 70 C Pin Grid Array 1 MHz to 10 MHz 10 0 MHz O C to 85 C IRC Suffix 1 MHz to 12 5 MHz 12 5 MHz O C to 85 C 5 MHz to 16 67 MHz 16 67 MHz O C to 85 C Plastic Lead 1 MHz to 10 MHz 10...

Page 133: ...l A2 A5 A9 A13 A15 A17 H 0 0 0 0 0 0 0 0 0 RXSYM2 RXSYMO TXCLK Al A4 A7 All GNO AlB G 0 o 0 0 0 BECl BEC2 SMREQ A21 A22 F 0 0 0 0 CLK BECO VOO A24 E 0 0 0 0 BR BG A26 A2B 0 o 0 0 0 BGACK lACK CS A31 C 0 0 0 0 0 0 0 0 IRQ OTACK NOT USED DO 06 09 012 GNO FCl B do 0 0 0 0 0 0 NC UOS AO 02 05 DB 011 015 FC3 A 0 0 0 0 0 0 0 0 AS 01 03 04 07 010 013 014 4 74 TXCLK RXCLK TXSYMO RXSYMO SMINO SMREQ RXSYM2 ...

Page 134: ... 0 090 0 110 0 013 0 019 O OSO BSC 0 026 0 032 0 020 0 025 1 1SO 1 156 1 ISO 1 156 0 042 0 048 0 042 0 048 0 042 0 056 0 020 2 10 1 110 1 130 0 040 2 10 DETAIL S NOTES 1 DUE TO SPACE LIMITATION CASE 780 01 SHALL BE REPRESENTED BY A GENERAL SMALLER CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 84 LEADS 2 DATUMS L M N AND p DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE ...

Page 135: ... AND TIS ADATUM SURFACE 2 POSITIONAL TOLERANCE FOR LEADS 84 PL cfJO 13 0 005 9 T A B I 3 DIMENSIONING AND TOLERANCING PER Y14 5M 1982 4 CONTROLLING DIMENSION INCH MILLIMETERS INCHES DIM MIN MAX MIN MAX A 27 43 1 080 B 27 43 1 080 C 2 03 2 67 0 080 0 105 D 0 43 0 61 0 017 0 024 G 2 54 BSC 0 100 BSC K 3 56 4 95 0 140 0 195 MC68824 USER S MANUAL ...

Page 136: ...tion addresses Explanation of error related functions are not presented here Descriptions may be found in the IEEE 802 4 standard A 2 STEADY STATE OPERATION TERMS This Station TS The address of the station that the discussion is in reference to Previous Station PS The address of the station that TS gets the token from Next Station NS The address of the station that TS passes the token to During st...

Page 137: ...rmation field is in multiples of slot time zero two four or six and is determined the first time by the two most significant bits in the station s address Having different lengths of the claim token frames is done in anticipation that more than one station will attempt to establish the logical ring at the same time After a station sends a claim token frame the station waits one slot time for its t...

Page 138: ...hin the four slot times the sending station assumes its successor has failed The sending station will now send a who follows frame with its successors address in the data field of the frame All the stations on the network compare this address to the address of their predecessor and if they match that station will send a IIset successor frame with its address in the data field The sending station n...

Page 139: ...ro with six being the highest access class LLC has eight access classes defined These eight access classes are mapped into the MAC access classes by the MAC ignoring the least significant bit The TBC always receives frames that are destined to it and places them in the appropriate priority queue The TBC only transmits out of enabled queues The user enables the queues in the transmit status area of...

Page 140: ...vel and phase lock by using a known pattern Preamble is also used to give stations a minimum amount of time to process a frame previously received The amount of preamble transmitted depends on the data rate and modulation scheme Preamble must always be a minimum of 2 microseconds regardless of the data rate and an integral number of octets must be sent Therefore on a 10 Mbitlsec network three octe...

Page 141: ...0 0 1 0 0 0 token 0 0 1 1 0 0 seLsuccessor Data frames are represented as follows Bits 0 First Bit Transmitted M M M p p p Most Significant Bit Where Frame Type E f o 1 LCC Data Frame 1 0 Reserved Former Systems Management 1 1 Reserved MAC Action M M M 0 0 0 Request with No Response 0 0 1 Request with Response 0 1 0 Response Priority P P P 1 1 1 Highest Priority 6 1 1 0 6 1 0 1 4 1 0 0 4 0 1 1 2 0...

Page 142: ...ted the TBC treats the last four bytes of data as the FCS The user may also choose to write the FCS to memory through the SET MODE 3 command The TBC can accept frames with an incorrect FCS by setting the receive error mask in the initialization table appropriately The term CRC cyclic redundancy check is used synony mously with FCS throughout this document B 1 7 End Delimiter The end delimiter ends...

Page 143: ...git paried in groups of two The bits within each octet or pair are transmitted from the least significant bit to the most significant bit For example an address supplied by IEEE is represented as follows FO 2E 15 6C 77 9B It would be transmitted onto the local area network as follows First Bit Transmitted 0000 1111 0111 0100 1010 1000 0011 0110 1110 1110 1101 1001 This address would appear in the ...

Page 144: ... 0036 IA Mask 1111 1111 1111 1000 FFF8 hex To cite a specific example if the destination address of an incoming frame is set to 0032 the operation for acceptance of the frame is performed by the TBC as follows 0032 DA ANDed with FFF8 lA Mask 0036 TS ANDed with FFF8 lA Mask Since the equation is true the frame is accepted A binary representation of the acceptance equation is shown below DA 0000 000...

Page 145: ...ddress Mask Bit o 3 4 9 10 15 16 21 22 010 Floor 2 001000 Cell 4 000011 Proj 1 000010 Dept 2 Proj 2 The equation for accepting a group address GA frame Destination Address DA AND GA Mask DA 47 Zeros Zeros Zeros Zeros Zeros 47 000 00000 To calculate the value for the group address mask field the logical OR of the group address is used For example if a station is a member of both projects 1 and 2 th...

Page 146: ...ended to be used are given in the MAP specification and include connecting two or more identical LANs multiplying the maximum allowable nodes and maximum allowable cable distances without affecting the token rotation times of each segment a bridge is not a repeater connecting LANs with different data rates connecting 10 Mbps 802 4 broadband to 5 Mbps 802 4 carrierband and connecting two different ...

Page 147: ... two most significant bits of the address differentiate which region the frame goes to the next two significant bits of the address differentiate which segment the frame goes to and the four least significant bits differentiate which station the frame goes to For simplicity in the following example we assume that only those eight bits form the address Bridges A and B recognize frames for regions 1...

Page 148: ...02 1 committee A table of translations is required at each station in some flat addressed bridging schemes such as IBM defined source routing In source routing the route taken by or chosen for a frame as it traverses the network is reflected in the routing information field which is imbedded in the frame itself Source routing is being proposed by the IEEE 802 5 committee for interconnection of 802...

Page 149: ...se When using source routing the routing field is a subset of the data field of the 802 4 standard The frame format is shown as follows NORMAL 802 4 FRAME SD FC DA SA DATA FCS ED SOURCE ROUTING IMPLEMENTED SD FC DA SA RI DATA FCS ED IG 1 The routing information RI field is present only when the SA field least significant bit referred to as the routing information indicator or RII bit is set to one...

Page 150: ...ecognize source routing RSR bit is set by the SET MODE 2 command the TBC provides source routing based frame reception in addition to normal address based frame reception The TBC does not by itself provide a bridge function but does receive and transmit frames containing the source routing fields as any other MAC frames Frames are copied based on recognition of a segment pair as described in route...

Page 151: ...cal to segment pairs meaning bridge numbers can be the same as long as they are not connecting the same two segments Source 10 SID is the identification of the segment where the frame comes from The target 10 TID is the identification of the segment where the frame is going to The source routing mask SR MASK is a two octet parameter defining which bits in the RDs are the segment number denoted by ...

Page 152: ...ferently routed frame by sending it back to the transmitting station The target host must change the RC field and put the frame into the transmit queue Each follows the route of its routing designator field in the opposite direction In these frames that are sent back the RII bit is set to one the RI field is as it arrived the broadcast field is set to OXX the D bit equals one the SA is the individ...

Page 153: ...MOTOROLA r R MC68824 USER S MANUAL ...

Page 154: ... the end delimiter ED to the start of TBC preamble and take into account the I O sampling delays in the TBC System Parameters Address Length 48 bits TBC mode bits are in their default state except predefined response mode is enabled in ring desired is enabled and all statistics are enabled Bus Width 16 bits Bus Latency one cycle Wait States none Commands none BD and FD pools are not empty with no ...

Page 155: ...es athree byte group addressed data frame not for the TBe and immediately after receives a token frame that is addressed to the TBe just after it has passed the token two station ring 8 The TBe receives a three byte data frame that is a broadcast address and immediately after receives a token frame that is addressed to the TBe just after it has passed the token two station ring 9 The TBe receives ...

Page 156: ......

Page 157: ... Commands II Buffer Structures II Signals II Bus Operation II TBC Interfaces II Electrical Specifications II Ordering Information and Mechanical Data III IEEE 802 4 Operation II Frame Formats and Addressing II Bridging Performance ...

Page 158: ...ications Also provided is ordering information and mechanical data to id the user in selecting the best part for his application The Motorola MC68824 Token Bus Controller is a silicon integrated circuit which implements the media access control MAC portion of the IEEE 802 4 standard This standard has been selected for the Manufacturing Automation Protocol MAP specification The MC68824 built in fea...

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