Motorola M5271EVB, User Manual, Page: 24 / 104

1-16 M5271EVB User’s Manual
Connectors and User Components
1.4.5 QSPI
The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral
interface with queued transfer capability. It will support up to 16 stacked transfers at one
time, minimizing CPU intervention between transfers. Transfer RAMs in the QSPI are
indirectly accessible using address and data registers.
Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued
Serial Module) implemented in the MC68332 processor.
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 147.1-Kbps to 18.75-Mbps at 75MHz.
• Programmable delays before and after transfers
• Programmable QSPI clock phase and polarity
• Supports wrap-around mode for continuous transfers
Please see the MCF5271 User’s Manual for more detail. The QSPI signals from the
MCF5271 device are brought out to expansion connector (J8).
1.5 Connectors and User Components
1.5.1 Daughter Card Expansion Connectors
Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5271 signals.
These connectors are ideal for interfacing to a custom daughter card or for simple probing
of processor signals. Below is a pinout description of these connectors.
Table 1-12. J3
Pin Signal Pin Signal
1 +5V 2 +5V
3 +3.3V 4 +3.3V
5 +3.3V 6 +3.3V
7 GND 8 GND
9 ERXD0 10 NC
11 ETXD1 12 NC
13 ETXD2 14 NC