Motorola DSP56309, User Manual

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11-10 DSP56309UM/D MOTOROLA
JTAG Port
TAP Controller
each location. This information is also available for factory process monitoring and for
failure mode analysis of assembled boards.
MotorolaÕs manufacturer identity is 00000001110. The customer part number consists of
two parts: Motorola design center number (bits 27:22) and a sequence number (bits
21:12). The sequence number is divided into two parts: core number (bits 21:17) and chip
derivative number (bits 16:12). Motorola Semiconductor Israel (MSIL) design center
number is 000110 and DSP56300 core number is 00001.
Once the IDCODE instruction is decoded, it selects the ID register, which is a 32-bit data
register. Since the Bypass register loads a logical 0 at the start of a scan cycle, whereas the
ID register loads a logical 1 into its LSB, examination of the first bit of data shifted out of
a component during a test data scan sequence immediately following exit from
Test-Logic-Reset controller state shows whether such a register is included in the design.
When the IDCODE instruction is selected, the operation of the test logic has no effect on
the operation of the on-chip system logic as required by the IEEE 1149.1 standard.
11.3.2.4 CLAMP (B[3:0] = 0011)
The CLAMP instruction is not included in the IEEE 1149.1 standard. It is provided as a
public instruction that selects the 1-bit bypass register as the serial path between TDI and
TDO while allowing signals driven from the component signals to be determined from
the BSR. During testing of ICs on PCB, it may be necessary to place static guarding
values on signals that control operation of logic not involved in the test. The EXTEST
instruction could be used for this purpose, but because it selects the BSR, the required
guarding signals would be loaded as part of the complete serial data stream shifted in,
both at the start of the test and each time a new test pattern is entered. Since the CLAMP
instruction allows guarding values to be applied using the BSR of the appropriate ICs
while selecting their bypass registers, it allows much faster testing than does the EXTEST
instruction. Data in the boundary scan cell remains unchanged until a new instruction is
shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also
asserts internal reset for the DSP56300 core system logic to force a predictable internal
state while performing external boundary scan operations.
11.3.2.5 HI-Z (B[3:0] = 0100)
The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a
manufacturerÕs optional public instruction to prevent having to backdrive the output
signals during circuit-board testing. When HI-Z is invoked, all output drivers, including
the two-state drivers, are turned off (i.e., high impedance). The instruction selects the
bypass register. The HI-Z instruction also asserts internal reset for the DSP56300 core
system logic to force a predictable internal state while performing external boundary
scan operations.