7-4
MPC180E Security Processor User’s Manual
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Operational Registers
7.1.4 Interrupt Mask Register (PKMR)
The Interrupt Mask Register allows the host processor to individually disable certain
interrupts. Normally, any change in the Status Register will cause a hardware interrupt on
the IRQ pin, as long as the Interrupt Enable (IE) bit in the Control Register is set to 1. If a
given bit of the PKMR is set to 1, the corresponding bit in the PKSR will no longer cause
the interrupt.
The PKMR is a read-write register. Its contents may be read or written by the host
processor.
0
10
11
12
13
14
15
Field
—
E_RDY
IRQ
OB
Z
DONE
Reset
0000_0000_0000_0001
R/W
R
Addr
0xB02
Figure 7-2. PKEU Status Register (PKSR)
Table 7-3. PKSR Field Descriptions
Bits
Name
Description
0–10
—
Reserved, should be cleared.
11
E_RDY
The E_RDY (exponent or k ready) bit indicates that the execution unit is ready to accept the
next 32-bit word of exponent data or point multiplier (k) data in the EXP(k) register. The host
processor may poll the status register to determine if this data needs to be provided or rely on
IRQ (if enabled) to signal when to look at the register to determine what data needs to be
provided. A write to the EXP(k) register will clear this bit as well as the associated IRQ (as long
as no other condition has also cause IRQ’s assertion). Note that there is approximately a two
cycle latency associated with the clearing of IRQ following a write to the EXP(k) register.
Since the EXP(k) register is double-buffered, the host response time, while important, is not
critical to meet maximum performance. At a minimum, the host will have 8 integer multiplies for
RSA or 8 point doubles for ECC to provide new data before adversely impacting the run time.
Refer to the run-time formulae (see Table 7-26) to determine the exact time available for the
target operating frequency.
For those instances where the host does not need to know the status of E_RDY (i.e. lower-level
routines), it is recommended that it mask this bit to prevent it from affecting the IRQ signal.
12
IRQ
The IRQ bit of the Status Register reflects the value of the IRQ output pin of the PKEU.
However, it will be set regardless of CR[IE].
13
OB
The OB bit of the Status Register is set to 1 if a read or write operation is to an unknown or
reserved address. The contents of the data bus on an out-of-bounds read is indeterminate.
14
Z
The ERR bit of the Status Register is set to 1 if a general error occurs in the PKEU. Any error
not associated with one of the Status Register bits will cause the ERR bit to assert.
15
DONE
The DONE bit of the Status Register is set to 1 when a branch to location 0 occurs. All of the
embedded routines cause the DONE bit to be asserted upon completion. Also, upon reset, the
DONE bit is set. This signifies to the host that the PKEU is ready for normal operation following
the reset. Until that time, the PKEU is busy with its boot procedure. This primarily entails
running the “clear all” routine, clearing all embedded RAM.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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