1-2
MPC180E Security Processor User’s Manual
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Architecture
•
Authentication
– MD4—
hashed message of 128 bits
– MD5—
hashed message of 128 bits
– SHA-1—hashed message of
160 bits
•
Random Number Generator
•
Glueless MPC8xx/82xx interface—50 and 66 MHz
•
DMA hardware handshaking signals
•
4-Kbit input and output FIFOs
•
1.8-V Vdd, 3.3 V I/O
•
100-pin LQFP package
1.2 System Architecture
The MPC180E works in load/store, memory-mapped systems. Figure 1-2 and Figure 1-2
show example system architectures. An external processor may execute application code
from its ROM and RAM, using RAM and optional nonvolatile memory (such as EEPROM)
for storing data. The MPC180E resides in the processor memory map; therefore, an
application requiring cryptographic functions simply writes to and reads from the
appropriate memory location.
The MPC180E interfaces to the MPC8xx system bus or to the local buss of the MPC8260.
Figure 1-1. Typical MPC8xx System Example
MPC860
SDRAM
I/O or Network
Interface
System Bus
EEPROM
MPC180E
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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