Motorola DigitalDNA ColdFire MCF5272 User Manual Download Page 451

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Chapter 19. Signal Descriptions

19-37

Power Supply Pins

19.18 Power Supply Pins

A pair of VDD/GND pins is dedicated to the on-chip USB transceiver.

16 bits

Reserved, do not use.

Table 19-9. MCF5272 High Impedance Mode Selection

HI-Z

Data Bus Width

Enable HI-Z mode, all pins are high impedance

Normal operation

Table 19-8. MCF5272 CS0 Memory Bus Width Selection (Continued)

BUSW1

BUSW0

CS0 Bus Width

Summary of Contents for DigitalDNA ColdFire MCF5272

Page 1: ...MCF5272UM D Rev 0 02 2001 MCF5272 ColdFire Integrated Microprocessor User s Manual ...

Page 2: ...ould create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any cl...

Page 3: ...s USB Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus Operation Appendix B Buffering and Impedence Matching Index Appendix A List of Memory Maps 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 A 6 20 B IND 21 23 22 IEEE 1149 1 Test Access Port JTAG Me...

Page 4: ...SB Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus Operation Appendix B Buffering and Impedence Matching Index Appendix A List of Memory Maps 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 A 6 20 B IND 21 23 22 IEEE 1149 1 Test Access Port JTAG Mecha...

Page 5: ...terrupt Inputs 1 6 1 2 3 UART Module 1 6 1 2 4 Timer Module 1 7 1 2 5 Test Access Port 1 7 1 3 System Design 1 7 1 3 1 System Bus Configuration 1 7 1 4 MCF5272 Specific Features 1 8 1 4 1 Physical Layer Interface Controller PLIC 1 8 1 4 2 Pulse Width Modulation PWM Unit 1 8 1 4 3 Queued Serial Peripheral Interface QSPI 1 8 1 4 4 Universal Serial Bus USB Module 1 9 Chapter 2 ColdFire Core 2 1 Featu...

Page 6: ... 2 20 2 2 2 7 Module Base Address Register MBAR 2 20 2 3 Integer Data Formats 2 20 2 4 Organization of Data in Registers 2 20 2 4 1 Organization of Integer Data Formats in Registers 2 21 2 4 2 Organization of Integer Data Formats in Memory 2 22 2 5 Addressing Mode Summary 2 22 2 6 Instruction Set Summary 2 23 2 6 1 Instruction Set Summary 2 26 2 7 Instruction Timing 2 29 2 7 1 MOVE Instruction Exe...

Page 7: ...amming ROMBAR for Power Management 4 7 4 5 Instruction Cache Overview 4 7 4 5 1 Instruction Cache Physical Organization 4 7 4 5 2 Instruction Cache Operation 4 9 4 5 2 1 Interaction with Other Modules 4 9 4 5 2 2 Cache Coherency and Invalidation 4 9 4 5 2 3 Caching Modes 4 9 4 5 2 3 1 Cacheable Accesses 4 10 4 5 2 3 2 Cache Inhibited Accesses 4 10 4 5 2 4 Reset 4 11 4 5 2 5 Cache Miss Fetch Algori...

Page 8: ...escriptions 5 22 5 5 3 3 1 Read A D Register rareg rdreg 5 23 5 5 3 3 2 Write A D Register wareg wdreg 5 24 5 5 3 3 3 Read Memory Location read 5 25 5 5 3 3 4 Write Memory Location write 5 26 5 5 3 3 5 Dump Memory Block dump 5 28 5 5 3 3 6 Fill Memory Block fill 5 30 5 5 3 3 7 Resume Execution go 5 32 5 5 3 3 8 No Operation nop 5 33 5 5 3 3 9 Read Control Register rcreg 5 34 5 5 3 3 10 Write Contr...

Page 9: ...Controller 7 1 Overview 7 1 7 2 Interrupt Controller Registers 7 2 7 2 1 Interrupt Controller Registers 7 3 7 2 2 Interrupt Control Registers ICR1 ICR4 7 4 7 2 2 1 Interrupt Control Register 1 ICR1 7 4 7 2 2 2 Interrupt Control Register 2 ICR2 7 5 7 2 2 3 Interrupt Control Register 3 ICR3 7 5 7 2 2 4 Interrupt Control Register 4 ICR4 7 6 7 2 3 Interrupt Source Register ISR 7 6 7 2 4 Programmable I...

Page 10: ... 9 10 1 SDRAM Read Accesses 9 17 9 10 2 SDRAM Write Accesses 9 19 9 10 3 SDRAM Refresh Timing 9 21 Chapter 10 DMA Controller 10 1 DMA Data Transfer Types 10 1 10 2 DMA Address Modes 10 2 10 3 DMA Controller Registers 10 2 10 3 1 DMA Mode Register DMR 10 2 10 3 2 DMA Interrupt Register DIR 10 4 10 3 3 DMA Source Address Register DSAR 10 5 10 3 4 DMA Destination Address Register DDAR 10 6 10 3 5 DMA...

Page 11: ... Watermark X_WMRK 11 21 11 5 12 FIFO Transmit Start Register X_FSTART 11 22 11 5 13 Receive Control Register R_CNTRL 11 23 11 5 14 Maximum Frame Length Register MAX_FRM_LEN 11 24 11 5 15 Transmit Control Register X_CNTRL 11 25 11 5 16 RAM Perfect Match Address Low ADDR_LOW 11 26 11 5 16 1 RAM Perfect Match Address High ADDR_HIGH 11 26 11 5 17 Hash Table High HASH_TABLE_HIGH 11 27 11 5 18 Hash Tabl...

Page 12: ...tion Number Register SPECR 12 13 12 3 2 9 USB Endpoint 0 Status Register EP0SR 12 13 12 3 2 10 USB Endpoint 0 IN Configuration Register IEP0CFG 12 14 12 3 2 11 USB Endpoint 0 OUT Configuration Register OEP0CFG 12 15 12 3 2 12 USB Endpoint 1 7 Configuration Register EPnCFG 12 16 12 3 2 13 USB Endpoint 0 Control Register EP0CTL 12 16 12 3 2 14 USB Endpoint 1 7 Control Register EPnCFG 12 19 12 3 2 15...

Page 13: ...uction 13 1 13 2 GCI IDL Block 13 3 13 2 1 GCI IDL B and D Channel Receive Data Registers 13 4 13 2 2 GCI IDL B and D Channel Transmit Data Registers 13 5 13 2 3 GCI IDL B and D Channel Bit Alignment 13 6 13 2 3 1 B Channel Unencoded Data 13 6 13 2 3 2 B Channel HDLC Encoded Data 13 7 13 2 3 3 D Channel HDLC Encoded Data 13 7 13 2 3 4 D Channel Unencoded Data 13 8 13 2 3 5 GCI IDL D Channel Conten...

Page 14: ...er PGMTA 13 28 13 5 15 GCI Monitor Channel Transmit Status Register PGMTS 13 28 13 5 16 GCI C I Channel Receive Registers P0GCIR P3GCIR 13 29 13 5 17 GCI C I Channel Transmit Registers P3GCIT P0GCIT 13 31 13 5 18 GCI C I Channel Transmit Status Register PGCITSR 13 31 13 5 19 D Channel Status Register PDCSR 13 32 13 5 20 D Channel Request Register PDRQR 13 33 13 5 21 Sync Delay Registers P0SDR P3SD...

Page 15: ...5 8 Programming Example 14 15 Chapter 15 Timer Module 15 1 Overview 15 1 15 2 Timer Operation 15 2 15 3 General Purpose Timer Registers 15 3 15 3 1 Timer Mode Registers TMR0 TMR3 15 3 15 3 2 Timer Reference Registers TRR0 TRR3 15 4 15 3 3 Timer Capture Registers TCR0 TCR3 15 5 15 3 4 Timer Counters TCN0 TCN3 15 5 15 3 5 Timer Event Registers TER0 TER3 15 5 Chapter 16 UART Modules 16 1 Overview 16 ...

Page 16: ...eceiver Clock Source 16 20 16 5 1 1 Programmable Divider 16 20 16 5 1 2 Calculating Baud Rates 16 21 16 5 1 2 1 CLKIN Baud Rates 16 21 16 5 1 2 2 External Clock 16 22 16 5 1 2 3 Autobaud Detection 16 22 16 5 2 Transmitter and Receiver Operating Modes 16 23 16 5 2 1 Transmitting 16 23 16 5 2 2 Receiver 16 25 16 5 2 3 Transmitter FIFO 16 26 16 5 2 4 Receiver FIFO 16 26 16 5 3 Looping Modes 16 28 16 ...

Page 17: ...4 Chapter 19 Signal Descriptions 19 1 Signal List 19 1 19 2 Address Bus A 22 0 SDRAM_ADR 13 0 19 16 19 3 Data Bus D 31 0 19 16 19 3 1 Dynamic Data Bus Sizing 19 17 19 4 Chip Selects CS7 SDCS CS6 AEN CS 5 1 CS0 19 17 19 5 Bus Control Signals 19 17 19 5 1 Output Enable Read OE RD 19 17 19 5 2 Byte Strobes BS 3 0 19 17 19 5 3 Read Write R W 19 19 19 5 4 Transfer Acknowledge TA PB5 19 19 19 5 5 Hi Z 1...

Page 18: ...ter Output Enable USB_TxEN PA5 19 24 19 10 7 USB Rx Data Output USB_RxD PA6 19 24 19 10 8 USB_D and USB_D 19 24 19 10 9 USB_CLK 19 24 19 10 10 INT1 USB Wake on Ring USB_WOR 19 24 19 11 Timer Module Signals 19 25 19 11 1 Timer Input 0 TIN0 19 25 19 11 2 Timer Output TOUT0 PB7 19 25 19 11 3 Timer Input 1 TIN1 PWM Mode Output 2 PWM_OUT2 19 25 19 11 4 Timer Output 1 TOUT1 PWM Mode Output 1 PWM_OUT1 19...

Page 19: ...est DREQ0 PA10 19 31 19 15 1 9 QSPI Chip Select 1 QSPI_CS1 PA11 19 31 19 15 2 GCI IDL TDM Port 1 19 31 19 15 2 1 GCI IDL Data Clock DCL1 GDCL1_OUT 19 31 19 15 2 2 GCI IDL Data Out DOUT1 19 31 19 15 2 3 GCI IDL Data In DIN1 19 31 19 15 2 4 GCI IDL Frame Sync FSC1 FSR1 DFSC1 19 32 19 15 2 5 D Channel Request DREQ1 PA14 19 32 19 15 2 6 D Channel Grant DGNT1_INT6 PA15_INT6 19 32 19 15 3 GCI IDL TDM Po...

Page 20: ...Bus Interface Types 20 10 20 6 1 Interface for FLASH SRAM Devices with Byte Strobes 20 10 20 6 2 Interface for FLASH SRAM Devices without Byte Strobes 20 15 20 7 Burst Data Transfers 20 20 20 8 Misaligned Operands 20 20 20 9 Interrupt Cycles 20 21 20 10 Bus Errors 20 22 20 11 Bus Arbitration 20 24 20 12 Reset Operation 20 24 20 12 1 Master Reset 20 25 20 12 2 Normal Reset 20 26 20 12 3 Software Wa...

Page 21: ...e Timing Specifications 23 13 23 4 2 Fast Ethernet AC Timing Specifications 23 15 23 4 2 1 MII Receive Signal Timing E_RxD 3 0 E_RxDV E_RxER and E_RxCLK 23 15 23 4 2 2 MII Transmit Signal Timing E_TxD 3 0 E_TxEN E_TxER E_TxCLK 23 16 23 4 2 3 MII Async Inputs Signal Timing CRS and COL 23 17 23 4 2 4 MII Serial Management Channel Timing MDIO and MDC 23 17 23 4 3 Timer Module AC Timing Specifications...

Page 22: ...xxii MCF5272 User s Manual CONTENTS Paragraph Number Title Page Number Appendix B Buffering and Impedance Matching ...

Page 23: ...ss Register ROMBAR 4 6 4 3 Instruction Cache Block Diagram 4 8 4 4 Cache Control Register CACR 4 13 4 5 Access Control Register Format ACRn 4 15 5 1 Processor Debug Module Interface 5 1 5 2 PSTCLK Timing 5 2 5 3 Example JMP Instruction Output on PST DDATA 5 5 5 4 Debug Programming Model 5 6 5 5 Address Attribute Trigger Register AATR 5 8 5 6 Address Breakpoint Registers ABLR ABHR 5 9 5 7 Configura...

Page 24: ...wdmreg Command Sequence 5 37 5 39 wdmreg BDM Command Format 5 37 5 41 Recommended BDM Connector 5 45 6 1 SIM Block Diagram 6 1 6 2 Module Base Address Register MBAR 6 4 6 3 System Configuration Register SCR 6 5 6 4 System Protection Register SPR 6 7 6 5 Power Management Register PMR 6 8 6 6 Activate Low Power Register ALPR 6 10 6 7 Device Identification Register DIR 6 12 6 8 Watchdog Reset Referen...

Page 25: ...de Register DMR 10 2 10 2 DMA Interrupt Register DIR 10 4 10 3 DMA Source Address Register DSAR 10 6 10 4 DMA Destination Address Register DDAR 10 6 10 5 DMA Byte Count Register DBCR 10 6 11 1 Ethernet Block Diagram 11 2 11 2 Fast Ethernet Module Block Diagram 11 2 11 3 Ethernet Frame Format 11 4 11 4 Ethernet Address Recognition Flowchart 11 8 11 5 Ethernet Control Register ECNTRL 11 12 11 6 I_MA...

Page 26: ...egister IEP0CFG 12 15 12 14 USB Endpoint 0 OUT Configuration Register 12 16 12 15 USB Endpoint 1 7 Configuration Register 12 16 12 16 USB Endpoint 0 Control Register EP0CTL 12 17 12 17 USB Endpoint 1 7 Control Register EPnCR 12 20 12 18 USB Endpoint 0 Interrupt Mask EP0IMR and General Endpoint 0 Interrupt Registers EP0ISR 12 22 12 19 USB Endpoints 1 7 Interrupt Status Registers EPnISR 12 24 12 20 ...

Page 27: ...ive Registers P0GCIR P3GCIR 13 29 13 29 GCI C I Channel Transmit Registers P0GCIT P3GCIT 13 31 13 30 GCI C I Channel Transmit Status Register PGCITSR 13 32 13 31 D Channel Status Register PDCSR 13 32 13 32 D Channel Request Registers PDRQR 13 33 13 33 Sync Delay Registers P0SDR P3SDR 13 34 13 34 Clock Select Register PCSR 13 35 13 35 Port 1 PLCR Configuration 13 37 13 36 Port 1 PLICR Configuration...

Page 28: ...IFO Registers UTFn 16 16 16 17 UART Receiver FIFO Registers URFn 16 16 16 18 UART Fractional Precision Divider Control Registers UFPDn 16 17 16 19 UART Input Port Registers UIPn 16 18 16 20 UART Output Port Command Registers UOP1 UOP0 16 18 16 21 UART Block Diagram Showing External and Internal Interface Signals 16 19 16 22 UART RS 232 Interface 16 20 16 23 Clocking Source Diagram 16 21 16 24 Tran...

Page 29: ...Address Hold EBI 11 32 Bit Port Internal Termination 20 18 20 15 Longword Write with Address Hold EBI 11 32 Bit Port Internal Termination 20 18 20 16 Longword Read with Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination 20 19 20 17 Longword Write with Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination 20 19 20 18 Example of a Misaligned Longword Transfer 20 ...

Page 30: ... 16 23 12 MII Transmit Signal Timing Diagram 23 17 23 13 MII Async Inputs Timing Diagram 23 17 23 14 MII Serial Management Channel Timing Diagram 23 18 23 15 Timer Timing 23 19 23 16 UART Timing 23 20 23 17 IDL Master Timing 23 21 23 18 IDL Slave Timing 23 23 23 19 GCI Slave Mode Timing 23 24 23 20 GCI Master Mode Timing 23 25 23 21 General Purpose I O Port Timing 23 26 23 22 USB Interface Timing ...

Page 31: ...ion Times 2 34 2 16 General Branch Instruction Execution Times 2 35 2 17 Bcc Instruction Execution Times 2 36 2 18 Exception Vector Assignments 2 37 2 19 Format Field Encoding 2 38 2 20 Fault Status Encodings 2 38 2 21 MCF5272 Exceptions 2 39 3 1 MAC Instruction Summary 3 4 4 1 Memory Map of Instruction Cache Registers 4 2 4 2 RAMBAR Field Description 4 3 4 3 Examples of Typical RAMBAR Settings 4 ...

Page 32: ...rvisor Mode Instructions 5 44 6 1 SIM Registers 6 3 6 2 MBAR Field Descriptions 6 5 6 3 SCR Field Descriptions 6 5 6 4 SPR Field Descriptions 6 7 6 5 PMR Field Descriptions 6 8 6 6 USB and USART Power Down Modes 6 10 6 7 Exiting Sleep and Stop Modes 6 11 6 8 DIR Field Descriptions 6 12 6 9 WRRR Field Descriptions 6 13 6 10 WIRR Field Descriptions 6 13 6 11 WER Field Descriptions 6 14 7 1 Interrupt...

Page 33: ...even Wire Mode Configuration 11 3 11 3 Ethernet Address Recognition 11 7 11 4 Transmission Errors 11 10 11 5 Reception Errors 11 10 11 6 FEC Register Memory Map 11 11 11 7 ECNTRL Field Descriptions 11 12 11 8 I_EVENT Field Descriptions 11 13 11 9 I_MASK Register Field Descriptions 11 14 11 10 IVEC Field Descriptions 11 15 11 11 R_DES_ACTIVE Register Field Descriptions 11 16 11 12 X_DES_ACTIVE Fiel...

Page 34: ...Descriptions 12 14 12 11 IEP0CFG Field Descriptions 12 15 12 12 EP0CTL Field Descriptions 12 17 12 13 EPnCR Field Descriptions 12 20 12 14 EP0IMR and EP0ISR Field Descriptions 12 22 12 15 EPnISR Field Descriptions 12 25 12 17 EPnDAT Field Descriptions 12 26 12 16 EPnIMR Field Descriptions 12 26 12 18 EPnDPR Field Descriptions 12 27 12 19 USB FIFO Access Timing 12 29 12 20 Example FIFO Setup 12 31 ...

Page 35: ...Field Descriptions 16 12 16 8 UACRn Field Descriptions 16 13 16 9 UISRn UIMRn Field Descriptions 16 14 16 10 UTFn Field Descriptions 16 16 16 11 URFn Field Descriptions 16 17 16 12 UFPDn Field Descriptions 16 17 16 13 UIPn Field Descriptions 16 18 16 14 UOP1 UOP0 Field Descriptions 16 18 16 15 UART Module Signals 16 19 16 16 Transmitter FIFO Status Bits 16 26 16 17 Receiver FIFO Status Bits 16 27 ...

Page 36: ...d Output Timing Specifications 23 5 23 7 Processor Bus Input Timing Specifications 23 6 23 8 Processor Bus Output Timing Specifications 23 8 23 9 Debug AC Timing Specification 23 12 23 10 SDRAM Interface Timing Specifications 23 13 23 11 MII Receive Signal Timing 23 15 23 12 MII Transmit Signal Timing 23 16 23 13 MII Async Inputs Signal Timing 23 17 23 14 MII Serial Management Channel Timing 23 17...

Page 37: ...t Register Memory Map A 3 A 7 QSPI Module Memory Map A 4 A 8 PWM Module Memory Map A 4 A 9 DMA Module Memory Map A 4 A 10 UART0 Module Memory Map A 5 A 11 UART1 Module Memory Map A 6 A 12 SDRAM Controller Memory Map A 7 A 13 Timer Module Memory Map A 7 A 14 PLIC Module Memory Map A 8 A 15 Ethernet Module Memory Map A 9 A 16 USB Module Memory Map A 10 ...

Page 38: ...xxxviii MCF5272 User s Manual TABLES Table Number Title Page Number ...

Page 39: ...ails of the ColdFire architecture Organization Following is a summary and brief description of the major sections of this manual Chapter 1 Overview includes general descriptions of the modules and features incorporated in the MCF5272 focussing in particular on new features Chapter 2 ColdFire Core provides an overview of the microprocessor core of the MCF5272 The chapter describes the organization ...

Page 40: ... Module describes the MCF5272 chip select implementation including the operation and programming model which includes the chip select address mask and control registers Chapter 9 SDRAM Controller describes configuration and operation of the synchronous DRAM controller component of the SIM including a general description of signals involved in SDRAM operations It provides interface information for ...

Page 41: ...s the use of the universal asynchronous synchronous receiver transmitters UARTs implemented on the MCF5272 including example register values for typical configurations Chapter 17 General Purpose I O Module describes the operation and programming model of the three general purpose I O GPIO ports on the MCF5272 The chapter details pin assignment direction control and data registers Chapter 18 Pulse ...

Page 42: ...ory mapped registers Appendix B Buffering and Impedance Matching provides some suggestions regarding interface circuitry between the MCF5272 and SDRAMs This manual also includes an index Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture General Information The following ...

Page 43: ...ction mnemonics are shown in lowercase italics Italics indicate variable command parameters Book titles in text are set in italics 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG FIELD Abbreviations for registers are shown in uppercase Specific bits fields or ranges appear in brackets For example RAMBAR BA identifies the base address field in the RAM base address reg...

Page 44: ... memory access DSP Digital signal processing EA Effective address EDO Extended data output DRAM FIFO First in first out GPIO General purpose I O I2C Inter integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last in first out LRU Least ...

Page 45: ...d POR Power on reset PQFP Plastic quad flat pack PWM Pulse width modulation QSPI Queued serial peripheral interface RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor transistor logic Tx Transmit UART Universal asynchronous synchronous receiver transmitter USB Universal serial bus Table i Acronyms and Abbreviated T...

Page 46: ...data register Rw Destination register w used for MAC instructions only Ry Rx Any source and destination registers respectively Xi index register i can be an address or data register Ai Di Register Names ACC MAC accumulator register CCR Condition code register lower byte of SR MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name DDATA Debug data port PST ...

Page 47: ...and is logically complemented Logical AND Logical OR Logical exclusive OR Shift left example D0 3 is shift D0 left 3 bits Shift right example D0 3 is shift D0 right 3 bits Source operand is moved to destination operand Two operands are exchanged sign extended All bits of the upper portion are made equal to the high order bit of the lower portion If condition then operations else operations Test th...

Page 48: ...ress Calculated effective address pointer Bit Bit selection example Bit 3 of D0 lsb Least significant bit example lsb of D0 LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero Table ii Notational Conventions Continued Instruction Operand Syn...

Page 49: ...n chip memories 4 Kbyte SRAM on CPU internal bus 16 Kbyte ROM on CPU internal bus 1 Kbyte instruction cache Power management Fully static operation with processor sleep and whole chip stop modes Very rapid response to interrupts from the low power sleep mode wake up feature Clock enable disable for each peripheral when not used Software controlled disable of external clock input for virtually zero...

Page 50: ...perand Fetch Address Generation Execute IFP OEP D 31 0 Instruction Address Generation Memory Instruction Bus SDRAM Controller External Bus Interface SYSTEM INTEGRATION MODULE SIM 32 Bit Address Bus 32 Bit Data Bus Interrupt Controller CS 7 0 8 8 8 4 ICRs MBAR PIWR CSORs CSBRs INT 6 1 6 DRAM Controller Outputs PIVR PITR ISR WRRR WIRR ALPR PMR System Control Base Address DIR Identification SDRAM Con...

Page 51: ...ports 16 256 Mbit devices External bus configurable for 16 or 32 bits width for SDRAM Glueless interface to SRAM devices with or without byte strobe inputs Programmable wait state generator Queued serial peripheral interface QSPI Full duplex three wire synchronous transfer Up to four chip selects available Master operation Programmable master bit rates Up to 16 preprogrammed transfers Timer module...

Page 52: ...temperature 0 70 C Operating frequency DC to 66 MHz from external CMOS oscillator Compact ultra low profile 196 ball molded plastic ball grid array package PGBA 1 2 MCF5272 Architecture This section briefly describes the MCF5272 core SIM UART and timer modules and test access port 1 2 1 Version 2 ColdFire Core Based on the concept of variable length RISC technology ColdFire combines the simplicity...

Page 53: ... power management features 1 2 2 1 External Bus Interface The external bus interface EBI handles the transfer of information between the internal core and memory peripherals or other processing elements in the external address space 1 2 2 2 Chip Select and Wait State Generation Programmable chip select outputs provide signals to enable external memory and peripheral circuits providing all handshak...

Page 54: ...ntered by the disabling of the external clock input and is achieved by software setting a bit in a control register Program execution stops after the current instruction In stop mode neither the core nor peripherals are active The MCF5272 consumes very little power in this mode To resume normal operation the external interrupts cause the power management logic to re enable the external clock input...

Page 55: ... when the timer reaches a set value Each unit has an 8 bit prescaler for deriving the clock input frequency from the system clock or external clock input The output pin associated with each timer has programmable modes To reduce power consumption the timer module can be disabled by software 1 2 5 Test Access Port For system diagnostics and manufacturing testing the MCF5272 includes user accessible...

Page 56: ...le generates a synchronous series of pulses The duty cycle of the pulses is under software control Its main features include the following Double buffered width register Variable divide prescale Three identical independent PWM modules Byte wide width register provides programmable control of duty cycle The PWM implements a simple free running counter with a width register and comparator such that ...

Page 57: ... and polarity Supports wrap around mode for continuous transfers 1 4 4 Universal Serial Bus USB Module The USB controller on the MCF5272 supports device mode data communications with a USB host typically a PC One host and up to 127 attached peripherals share USB bandwidth through a host scheduled token based protocol The USB uses a tiered star topology with a hub at the center of each star Each wi...

Page 58: ...1 10 MCF5272 User s Manual MCF5272 Specific Features ...

Page 59: ...ent decoupled pipelines two stage instruction fetch pipeline IFP and two stage operand execution pipeline OEP Three longword FIFO buffer provides decoupling between the pipelines 32 bit internal address bus supporting 4 Gbytes of linear address space 32 bit data bus 16 user accessible 32 bit wide general purpose registers Supervisor user modes for system protection Vector base register to relocate...

Page 60: ...generation execute AGEX calculates the operand address or performs the execution of the instruction Figure 2 1 ColdFire Pipeline 2 1 1 1 Instruction Fetch Pipeline IFP The IFP generates instruction addresses and fetches Because the fetch and execution pipelines are decoupled by a 3 longword FIFO buffer the IFP can prefetch instructions before the OEP needs them minimizing stalls Instruction Instru...

Page 61: ...tively combines a memory to register operation with a store operation 2 1 1 2 1 Illegal Opcode Handling On Version 2 ColdFire implementations only some illegal opcodes 0x0000 and 0x4AFC are decoded and generate an illegal instruction exception Additionally attempting to execute an illegal line A or line F opcode generates unique exception types If any other unsupported opcode is executed the resul...

Page 62: ... operand producing a 32 bit quotient 32 bit operand 32 bit operand producing a 32 bit remainder 2 1 2 Debug Module Enhancements The ColdFire processor core debug interface supports system integration in conjunction with low cost development tools Real time trace and debug information can be accessed through a standard interface which allows the processor and system to be debugged at full speed wit...

Page 63: ...ogramming model using the WDEBUG instruction 2 2 Programming Model The MCF5272 programming model consists of three instruction and register groups user MAC also user mode and supervisor shown in Figure 2 2 User mode programs are restricted to user and MAC instructions and programming models Supervisor mode system software can reference all user mode and MAC instructions and registers and additiona...

Page 64: ...gisters A0 A6 The address registers A0 A6 can be used as software stack pointers index registers or base address registers and may be used for word and longword operations 31 0 D0 Data registers D1 D2 D3 D4 D5 D6 D7 31 0 A0 Address registers A1 A2 A3 A4 A5 A6 A7 Stack pointer PC Program counter CCR Condition code register 31 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register 15...

Page 65: ...ated with the target instruction For some instructions the PC specifies the base address for PC relative operand addressing modes 2 2 1 5 Condition Code Register CCR The CCR Figure 2 4 occupies SR 7 0 as shown in Figure 2 3 CCR 4 0 are indicator flags based on results generated by arithmetic operations 7 6 5 4 3 2 1 0 Field X N Z V C Reset 000 Undefined R W R R W R W R W R W R W Figure 2 4 Conditi...

Page 66: ...ment operating system functions and provide memory and I O control The supervisor programming model provides access to the user registers and additional supervisor registers which include the upper byte of the status register SR the vector base register VBR and registers for configuring attributes of the address space connected to the Version 2 processor core Most supervisor mode registers are acc...

Page 67: ...er SR Table 2 3 Status Field Descriptions Bits Name Description 15 T Trace enable When T is set the processor performs a trace exception after every instruction 13 S Supervisor user state Indicates whether the processor is in supervisor or user mode 0 User mode 1 Supervisor mode 12 M Master interrupt state Cleared by an interrupt exception It can be set by software during execution of the RTE or m...

Page 68: ...ule and indicates the types of references mapped to it The RAMBAR includes a base address write protect bit address space mask bits and an enable The RAM base address must be aligned on a 0 modulo 4 Kbyte boundary See Section 4 3 2 1 SRAM Base Address Register RAMBAR 2 2 2 7 Module Base Address Register MBAR The module base address register MBAR defines the logical base address for the memory mapp...

Page 69: ...tire longword operand is used depending on the operation size Word length source operands are sign extended to 32 bits and then used in the operation with an address register destination When an address register is a destination the entire register is affected regardless of the operation size Figure 2 8 shows integer formats for address registers The size of control registers varies according to f...

Page 70: ...ands Alterable addressing modes refer to alterable writable data operands Control addressing modes refer to memory operands without an associated size These categories sometimes combine to form more restrictive categories Two combined classifications are alterable memory both alterable and memory and data alterable both alterable and data Twelve of the most commonly used effective addressing modes...

Page 71: ...ax Mode Field Reg Field Category Data Memory Control Alterable Register direct Data Address Dn An 000 001 reg no reg no X X X Register indirect Address Address with Postincrement Address with Predecrement Address with Displacement An An An d16 An 010 011 100 101 reg no reg no reg no reg no X X X X X X X X X X X X X X Address register indirect with scaled index 8 bit displacement d8 An Xi SF 110 re...

Page 72: ... Xi index register i can be an address or data register Ai Di Register Names ACC MAC accumulator register CCR Condition code register lower byte of SR MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Names DDATA Debug data port PST Processor status port Miscellaneous Operands data Immediate data following the 16 bit operation word of the instruction ea Ef...

Page 73: ...it of the lower portion If condition then operations else operations Test the condition If the condition is true the operations in the then clause are performed If the condition is false and the optional else clause is present the operations in the else clause are performed If the condition is false and the else clause is omitted the instruction performs no operation Refer to the Bcc instruction d...

Page 74: ...ND Dy ea x ea y Dx L L Source destination destination ANDI data Dx L Immediate data destination destination ASL Dy Dx data Dx L L X C Dx Dy 0 X C Dx data 0 ASR Dy Dx data Dx L L MSB Dx Dy X C MSB Dx data X C Bcc label B W If condition true then PC 2 dn PC BCHG Dy ea x data ea 1 x B L B L bit number of destination Z Bit of destination BCLR Dy ea x data ea 1 x B L B L bit number of destination Z 0 b...

Page 75: ...lted state JMP ea 3 y Unsized Address of ea PC JSR ea 3 y Unsized SP 4 SP next sequential PC SP ea PC LEA ea 3 y Ax L ea Ax LINK Ax d16 W SP 4 SP Ax SP SP Ax SP d16 SP LSL Dy Dx data Dx L L X C Dx Dy 0 X C Dx data 0 LSR Dy Dx data Dx L L 0 Dx Dy X C 0 Dx data X C MAC Ry RxSF L W W L L L L L ACC Ry Rx 1 1 ACC ACC Ry Rx 1 1 ACC ea y MASK Rw MACL Ry RxSF ea 1 y Rw L W W L L L L L L L ACC Ry Rx 1 1 AC...

Page 76: ... OR ea y Dx Dy ea x L Source destination destination ORI data Dx L Immediate data destination destination PEA ea 3 y L SP 4 SP Address of ea SP PULSE none Unsized Set PST 0x4 REMS ea 1 Dx L Dx ea y Dw 32 bit remainder Signed operation REMU ea 1 Dx L Dx ea y Dw 32 bit remainder Unsigned operation RTS none Unsized SP PC SP 4 SP Scc Dx B If condition true then 1s destination Else 0s destination SUB e...

Page 77: ...ruction is a supervisor mode instruction however it can be configured to allow user mode execution by setting CSR UHE Table 2 8 Supervisor Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation CPUSHL bc Ax Unsized Invalidate instruction cache line HALT1 1 The HALT instruction can be configured to allow user mode execution by setting CSR UHE none Unsized Enter halted state ...

Page 78: ... Instruction Execution Times The execution times for the MOVE B W L instructions are shown in the next tables Table 2 12 shows the timing for the other generic move operations NOTE For all tables in this section the execution time of any instruction using the PC relative effective addressing modes is equivalent to the time using comparable An relative mode ET with ea d16 PC equals ET with ea d16 A...

Page 79: ...1 3 1 1 3 1 1 4 1 1 3 1 1 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 Ay 3 1 0 31 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 d16 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 Ay Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 xxx w 3 1 0 3 1 1 3 1 1 3 1 1 xxx l 3 1 0 3 1 1 3 1 1 3 1 1 d16 PC 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 PC Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 xxx 1 0 0 3 0 1 3 0 1 3 0 1 Table 2 11 Move Long Execution Times Source Destina...

Page 80: ...0 0 1 0 0 move l ea MACSR 2 0 0 2 0 0 move l ea MASK 1 0 0 1 0 0 move l ACC Rx 1 0 0 move l MACSR CCR 1 0 0 move l MACSR Rx 1 0 0 move l MASK Rx 1 0 0 Table 2 13 One Operand Instruction Execution Times Opcode ea Effective Address Rn An An An d16 An d8 An Xi SF xxx wl xxx clr b ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 clr w ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 clr l ea 1 0 0 1 0 1 1 0 1...

Page 81: ...1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 bchg imm ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 bclr Dy ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 bclr imm ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 bset Dy ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 bset imm ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 btst Dy ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 btst imm ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 cmp l ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0...

Page 82: ...0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 or l Dy ea 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 or l imm Dx 1 0 0 rems l ea Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 remu l ea Dx 35 0 0 35 1 0 35 1 0 35 1 0 35 1 0 sub l ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 sub l Dy ea 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 subi l imm Dx 1 0 0 subq l imm ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 subx l Dy Dx 1 0 0 Tabl...

Page 83: ...ug l ea 5 2 0 5 2 0 1 n is the number of registers moved by the MOVEM opcode 2 PEA execution times are the same for d16 PC 3 PEA execution times are the same for d8 PC Xi SF 4 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts Table 2 16 General Branch Instruction Execution Times Opcode ea Effective Address Rn An An An d16 An d8 An Xi S...

Page 84: ...rforms this calculation based on the exception type For interrupts the processor performs an interrupt acknowledge IACK bus cycle to obtain the vector number from a peripheral device The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address 3 The processor saves the current context by creating an exception stack frame on the system stack ColdFi...

Page 85: ...ed in the status register Table 2 18 Exception Vector Assignments Vector Numbers Vector Offset Hex Stacked Program Counter 1 1 The term fault refers to the PC of the instruction that caused the exception The term next refers to the PC of the instruction that immediately follows the instruction that caused the fault Assignment 0 000 Initial stack pointer 1 004 Initial program counter 2 008 Fault Ac...

Page 86: ...ve existed when the exception occurred Fault status field The 4 bit field FS 3 0 at the top of the system stack is defined for access and address errors along with interrupted debug service routines See Table 2 20 31 28 27 26 25 18 17 16 15 0 A7 Format FS 3 2 Vector 7 0 FS 1 0 Status Register 0x04 Program Counter 31 0 Figure 2 10 Exception Stack Frame Form Table 2 19 Format Field Encoding Original...

Page 87: ...dingly the PC contained in the exception stack frame represents the location in the program when the access error is signaled not necessarily the instruction causing the fault All programming model updates associated with the write instruction are complete The NOP instruction can be used to help identify write access errors A NOP is not executed until all previous operations including any pending ...

Page 88: ...ition SR 15 in the exception stack frame asserted and pass control to the trace handler before returning from the original exception Debug Interrupt Caused by a hardware breakpoint register trigger Rather than generating an IACK cycle the processor internally calculates the vector number 12 Additionally the M bit and the interrupt priority mask fields of the SR are unaffected by the interrupt See ...

Page 89: ...visor mode by setting SR S and disables tracing by clearing SR T This exception also clears SR M and sets the processor s interrupt priority mask in the SR to the highest level level 7 Next the VBR is initialized to 0x0000_0000 Configuration registers controlling the operation of all processor local memories cache and RAM modules on the MCF5272 are invalidated disabling the memories Note Other imp...

Page 90: ...2 42 MCF5272 User s Manual Exception Processing Overview ...

Page 91: ... addition to a full set of extensions for signed and unsigned integers plus signed fixed point fractional input operands The MAC unit provides functionality in three related areas Signed and unsigned integer multiplies Multiply accumulate operations supporting signed unsigned and signed fractional operands Miscellaneous register operations Each of the three areas of support is addressed in detail ...

Page 92: ...e DSP engine would be excessive in an embedded environment In striking a middle ground between speed size and functionality the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions Specifically the multiplier array is optimized for single cycle 16 x 16 multiplies producing a 32 bit result with a possible accumulation cycle following This...

Page 93: ...tions using signed or unsigned operands These MAC operations treat the operands as one of the following formats Signed integers Unsigned integers Signed fixed point fractional numbers To maintain compactness the MAC module is optimized for 16 bit multiplications Two 16 bit operands produce a 32 bit product Longword operations are performed by reusing the 16 bit multiplier array at the expense of a...

Page 94: ...y operations defined by the baseline ColdFire architecture as well as the new multiply accumulate instructions Table 3 1 summarizes the MAC unit instruction set Table 3 1 MAC Instruction Summary Instruction Mnemonic Description Multiply Signed MULS ea y Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU ea y Dx Multiplies two unsigned operands yielding an unsigned re...

Page 95: ...nificant bit Two s complement signed fractional In an N bit number the first bit is the sign bit The remaining bits signify the first N 1 bits after the binary point Given an N bit number aN 1aN 2aN 3 a2a1a0 its value is given by the following formula This format can represent numbers in the range 1 operand 1 2 N 1 For words and longwords the greatest negative number that can be represented is 1 w...

Page 96: ...3 6 MCF5272 User s Manual MAC Instruction Execution Timings ...

Page 97: ...AM ROM and cache controllers This approach is required because the controllers are memory mapped devices and the hit miss determination is made concurrently with the read data access Power dissipation can be minimized by configuring the ROM and SRAM base address registers ROMBAR and RAMBAR to mask unused address spaces whenever possible If the access address is mapped into the region defined by th...

Page 98: ...k can be set to any 4 Kbyte address boundary within the 4 Gbyte address space The memory is ideal for storing critical code or data structures or for use as the system stack Because the SRAM module is physically connected to the processor s high speed local bus it can quickly service core initiated accesses or memory referencing commands from the debug module Section 4 1 Interactions between Local...

Page 99: ...AR can be accessed only in supervisor mode using the MOVEC instruction with an Rc value of 0xC04 Figure 4 1 SRAM Base Address Register RAMBAR RAMBAR fields are described in Table 4 2 31 12 11 9 8 7 6 5 4 3 2 1 0 Field BA WP C I SC SD UC UD V Reset 0 R W W for CPU R W for debug Address CPU space 0xC04 Table 4 2 RAMBAR Field Description Bits Name Description 31 12 BA Base address SRAM module base ad...

Page 100: ... the SRAM it may be appropriate to load a revised value into RAMBAR with new write protect and address space mask attributes These attributes consist of the write protect and address space mask fields The ColdFire processor or an external BDM emulator using the debug module can perform this initialization 5 1 C I SC SD UC UD Address space masks ASn These fields allow certain types of accesses to b...

Page 101: ...ower Management 4 4 ROM Overview The ROM modules has the following features 16 Kbyte ROM organized as 4K x 32 bits Contains data tables for soft HDLC high level data link control DTMF dual tone multiple frequency detection and tone generation The ROM does not contain instructions The ROM contents are not customizeable Single cycle access Physically located on ColdFire core s high speed local bus B...

Page 102: ...space 13 6 Reserved should be cleared 5 1 C I SC SD UC UD Address space masks ASn Allows specific address spaces to be enabled or disabled placing internal modules in a specific address space If an address space is disabled an access to the register in that address space becomes an external bus access and the module resource is not accessed These bits are useful for power management as described i...

Page 103: ...le cache miss fetch algorithm 4 5 1 Instruction Cache Physical Organization The instruction cache Figure 4 3 is a direct mapped single cycle memory organized as 64 lines each containing 16 bytes Memory consists of a 64 entry tag array containing addresses and a valid bit and a 1 Kbyte instruction data array organized as 64 x 128 bits The two memory arrays are accessed in parallel bits 9 4 of the i...

Page 104: ...mediately without waiting for the entire line to be fetched If the referenced address is not contained in the memory array or the line fill buffer the instruction cache initiates the required external fetch operation In most situations this is a 16 byte line sized burst reference Hardware is nonblocking meaning the ColdFire core s local bus is released after the initial access of a miss Thus the c...

Page 105: ...ences for accesses to cached instructions Therefore software must maintain cache coherency by invalidating the appropriate cache entries after modifying code segments Cache invalidation can be performed in the two following ways Setting CACR CINVA forces the entire instruction cache to be marked as invalid The invalidation operation requires 64 cycles because the cache sequences through the entire...

Page 106: ...ed data is given immediately to the processor without waiting for the three remaining longwords to reach the cache 4 5 2 3 2 Cache Inhibited Accesses Memory regions can be designated as cache inhibited which is useful for memory containing targets such as I O devices and shared data structures in multiprocessing systems Do not cache memory mapped registers for example registers shown with an MBAR ...

Page 107: ... CACR CENB a cacheable instruction fetch that misses in both the tag memory and the line fill buffer generates an external fetch The size of the external fetch is determined by the value contained in CACR CLNF and the miss address Table 4 8 shows the relationships between the CLNF bits the miss address and the size of the external fetch Depending on the run time characteristics of the application ...

Page 108: ...isters ACR0 ACR1 Table 4 7 shows the memory map of the CACR andACRs These registers have the following characteristics The CACR and ACRs can be accessed only in supervisor mode using the MOVEC instruction with an Rc value of 0x002 CACR 0x004 ACR0 and 0x005 ACR1 Addresses not assigned to the registers and undefined register bits are reserved for future expansion Write accesses to these reserved add...

Page 109: ...r is in background debug mode BDM Table 4 8 describes CACR fields Table 4 7 Memory Map of Instruction Cache Registers Address using MOVEC Name Width Description Reset Value 0x002 CACR 32 Cache control register 0x0000 0x004 ACR0 32 Access control register 0 0x0000 0x005 ACR1 32 Access control register 1 0x0000 31 30 29 28 27 26 25 24 23 16 Field CENB CDPI CFRZ CINVA Reset 0000_0000_0000_0000 R W Wr...

Page 110: ...uffer by a burst access same as a line fill They stay in the buffer until they are displaced so subsequent accesses may not appear on the external bus Note that this feature can cause a coherency problem for self modifying code If CEIB 1 and a cache inhibited access uses the fill buffer instructions remain valid in the fill buffer until a cache invalidate all instruction another cache inhibited bu...

Page 111: ...line access offsets CLNF Longword Address Bits 00 01 10 11 00 Line Line Line Longword 01 Line Line Longword Longword 1x Line Line Line Line 31 24 23 16 15 14 13 12 7 6 5 4 3 2 1 0 Field BA BAM EN SM CM BWE WP Reset 0000_0000_0000_0000 R W Write R W by debug module Rc ACR0 0x004 ACR1 0x005 Figure 4 5 Access Control Register Format ACRn Table 4 9 ACRn Field Descriptions Bits Name Description 31 24 B...

Page 112: ...y be more difficult For the ColdFire CPU reporting access errors on operand writes is always imprecise enabling buffered writes further decouples the write instruction from the signaling of the fault 0 Termination of an operand write cycle on the processor s local bus is delayed until the external bus cycle is completed 1 A write cycle on the local bus is terminated immediately and the operation i...

Page 113: ...BDM the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers The external emulator uses a three pin serial full duplex channel See Section 5 5 Background Debug Mode BDM and Section 5 4 Programming Model Real time debug support BDM requires the processor to be halted which many real time embedded applications cannot do Debug interrupts le...

Page 114: ... state Development Serial Input DSI Internally synchronized input that provides data input for the serial communication port to the debug module Development Serial Output DSO Provides serial output communication for debug module responses DSO is registered internally Breakpoint BKPT Input used to request a manual breakpoint Assertion of BKPT puts the processor into a halted state after the current...

Page 115: ... display the target address of such instructions in sequential nibble increments across multiple processor clock cycles as described in Section 5 3 1 Begin Execution of Taken Branch PST 0x5 Two 32 bit storage elements form a FIFO buffer connecting the processor s high speed local bus to the external development system through PST 3 0 and DDATA 3 0 The buffer captures branch target addresses and ce...

Page 116: ...WDDATA operand size 0x5 0101 Begin execution of taken branch For some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marker value preceding the DDATA nibble that begins the data output See Section 5 3 1 Begin Execution of Taken Branch PST 0x5 0x6 0110 Reserved 0x7 0111 Begin execut...

Page 117: ... or 4 bytes Another example of a variant branch instruction would be a JMP A0 instruction Figure 5 3 shows when the PST and DDATA outputs that indicate when a JMP A0 executed assuming the CSR was programmed to display the lower 2 bytes of an address Figure 5 3 Example JMP Instruction Output on PST DDATA PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2 byte address Thus th...

Page 118: ...ntain a 5 bit field DRc that specifies the register as shown in Table 5 3 Table 5 3 BDM Breakpoint Registers DRc 4 0 Register Name Abbreviation Initial State Page 0x00 Configuration status register CSR 0x0000_0000 p 5 9 0x01 0x05 Reserved 0x06 Address attribute trigger register AATR 0x0000_0005 p 5 7 0x07 Trigger definition register TDR 0x0000_0000 p 5 13 0x08 Program counter breakpoint register P...

Page 119: ...ribute Trigger Register AATR The address attribute trigger register AATR Figure 5 5 defines address attributes and a mask to be matched in the trigger The register value is compared with address attribute signals from the processor s local high speed bus as defined by the setting of the trigger definition register TDR 0x09 Program counter breakpoint mask register PBMR p 5 12 0x0A 0x0B Reserved 0x0...

Page 120: ...local bus 6 5 SZ Size Compared to the processor s local bus size signals 00 Longword 01 Byte 10 Word 11 Reserved 4 3 TT Transfer type Compared with the local bus transfer type signals 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Acknowledge CPU space access These bits also define the TT encoding for BDM memory commands In this case the 01 encoding indicates an external or DMA ...

Page 121: ...from the programming model It can be read from and written to through the BDM port CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands 31 0 Field Address Reset R W Write only ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port...

Page 122: ...r If TRG is set a hardware breakpoint halted the processor core and forced entry into BDM Reset the debug GO command or reading CSR clear TRG 25 HALT Processor halt If HALT is set the processor executed a HALT and forced entry into BDM Reset the debug GO command or reading CSR clear HALT 24 BKPT Breakpoint assert If BKPT is set BKPT was asserted forcing the processor into BDM Reset the debug GO co...

Page 123: ...tes in pipelined or mode or not 0 Pipelined mode 1 Nonpipelined mode The processor effectively executes one instruction at a time with no overlap This adds at least 5 cycles to the execution time of each instruction Given an average execution latency of 1 6 throughput in non pipeline mode would be 6 6 approximately 25 or less of pipelined performance Regardless of the NPL state a triggered PC brea...

Page 124: ...BMR is accessible in supervisor mode as debug control register 0x0F using the WDEBUG instruction and via the BDM port using the WDMREG command DRc 4 0 0x0E DBR 0x0F DBMR Figure 5 8 Data Breakpoint Mask Registers DBR and DBMR Table 5 9 DBR Field Descriptions Bits Name Description 31 0 Data Data breakpoint value Contains the value to be compared with the data value from the processor s local bus as ...

Page 125: ... first level trigger 31 0 Field Program Counter Reset R W Write PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 5 5 3 3 Command Set Descriptions DRc 4 0 0x08 Figure 5 9 Program Counter Breakpoint Register PBR Table 5 12 PBR Field Descriptions Bits Name Description 31 0 A...

Page 126: ...R EAL EPC PCI Reset 0000_0000_0000_0000 R W Write only Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command DRc 4 0 0x07 Figure 5 11 Trigger Definition Register TDR Table 5 14 TDR Field Descriptions Bits Name Description 31 30 TRC Trigger response control Determines how the processor responds to a completed trig...

Page 127: ...byte of the low order word 23 7 EDU M Upper middle data byte Low order byte of the high order word 22 6 EDU U Upper upper data byte High order byte of the high order word 21 5 DI Data breakpoint invert Provides a way to invert the logical sense of all the data breakpoint comparators This can develop a trigger based on the occurrence of a data value other than the DBR contents 20 18 4 2 EAx Enable ...

Page 128: ...the sample time the processor suspends execution and enters the halted state The assertion of BKPT should be considered in the following two special cases After the system reset signal is negated the processor waits for 16 processor clock cycles before beginning reset exception processing If the BKPT input is asserted within eight cycles after RSTI is negated the processor enters the halt state si...

Page 129: ...I is sampled and DSO is driven Figure 5 12 BDM Serial Interface Timing DSCLK and DSI are synchronized inputs DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI DSO is delayed from the DSCLK enabled CLK rising edge registered after a BDM state machine state change All events in the debug module s serial state machine are based on the proces...

Page 130: ...us of CPU generated messages listed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock periods S Data Message 0 xxxx Valid data transfer 0 0xFFFF Status OK 1 0x0000 Not ready with response come again 1 0x0001 Error Terminated bus cycle data invalid 1 0xFFFF Illegal command...

Page 131: ...3 3 0x1900 byte 0x1940 word 0x1980 lword Write memory location WRITE Write the operand data to the memory location specified by the longword address Steal 5 5 3 3 4 0x1800 byte 0x1840 word 0x1880 lword Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result A DUMP command retrieves...

Page 132: ... address data or operand data 15 10 9 8 7 6 5 4 3 2 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 5 15 BDM Command Format Table 5 18 BDM Field Descriptions Bit Name Description 15 10 Operation Specifies the command These values are listed in Table 5 17 9 0 Reserved 8 R W Direction of operand transfer 0 Data is written to the CPU or to memory from the development system 1 The t...

Page 133: ...red In cycle 2 the development system supplies the high order 16 address bits The debug module returns a not ready response unless the received command is decoded as unimplemented which is indicated by the illegal command encoding If this occurs the development system should retransmit the command COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH ORDER 16 BIT...

Page 134: ...ng a byte sized memory read operation the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits The next command s opcode is sent to the debug module during the final transfer If a memory or register access is terminated with a bus error the error status S 1 DATA 0x0001 is returned instead of result data 5 5 3 3 Command Set Descriptions The followi...

Page 135: ...re is not halted Command Result Formats Command Sequence Figure 5 18 RAREG RDREG Command Sequence Operand Data None Result Data The contents of the selected register are returned as a longword value most significant word first 15 12 11 8 7 4 3 2 0 Command 0x2 0x1 0x8 A D Register Result D 31 16 D 15 0 Figure 5 17 RAREG RDREG Command Format XXX MS RESULT NEXT CMD LS RESULT RAREG RDREG XXX BERR NEXT...

Page 136: ...equence Figure 5 20 WAREG WDREG Command Sequence Operand Data Longword data is written into the specified address or data register The data is supplied most significant word first Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete 15 12 11 8 7 4 3 2 0 0x2 0x0 0x8 A D Register D 31 16 D 15 0 Figure 5 19 WAREG WDREG Command Format ...

Page 137: ...sults return 16 bits of data longword results return 32 Bytes are returned in the LSB of a word result the upper byte is undefined 0x0001 S 1 is returned if a bus error occurs 15 12 11 8 7 4 3 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0x4 0x0 A 31 16 A 15 0 Result D 15 0 Longword Command 0x1 0x9 0x8 0x0 A 31 16 A 15 0 Result D 31 16 D 15 0 Figu...

Page 138: ...T TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Formats 15 12 11 8 7 4 3 1 Byte 0x1 0x8 0x0 0x0 A 31 16 A 15 0 X X X X X X X X D 7 0 Word 0x1 0x8 0x4 0x0 A 31 16 A 15 0 D 15 0 Longword 0x1 0x8 0x8 0x0 A 31 16 A 15 0 D 31 16 D 15 0 Figure 5 23 WRITE Command Format ...

Page 139: ...ent as 16 and 32 bits respectively Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete A value of 0x0001 with S set is returned if a bus error occurs MS ADDR NOT READY LS ADDR NOT READY WRITE B W NEXT CMD NOT READY XXX NOT READY XXX XXX BERR CMD COMPLETE NEXT CMD WRITE MEMORY LOCATION DATA NOT READY MS ADDR NOT READY LS ADDR NOT R...

Page 140: ... address perform the memory read increment it by the current operand size and store the updated address in the temporary register NOTE DUMP does not check for a valid address it is a valid command only when preceded by NOP READ or another DUMP command Otherwise an illegal command response is returned NOP can be used for intercommand padding without corrupting the address pointer The size field is ...

Page 141: ...ificant byte of a word result Word results return 16 bits of significant data longword results return 32 bits A value of 0x0001 with S set is returned if a bus error occurs XXX NOT READY NEXT CMD RESULT XXX BERR XXX ILLEGAL NEXT CMD NOT READY NEXT CMD NOT READY READ MEMORY LOCATION DUMP B W XXX NOT READY NEXT CMD MS RESULT XXX BERR XXX ILLEGAL NEXT CMD NOT READY NEXT CMD NOT READY READ MEMORY LOCA...

Page 142: ... store the updated address in the temporary register If an initial WRITE is not executed preceding the first FILL command the illegal command response is returned NOTE The FILL command does not check for a valid address FILL is a valid command only when preceded by another FILL a NOP or a WRITE command Otherwise an illegal command response is returned The NOP command can be used for intercommand p...

Page 143: ... 32 bits respectively Result Data Command complete status 0xFFFF is returned when the register write is complete A value of 0x0001 with S set is returned if a bus error occurs NEXT CMD NOT READY NOT READY XXX BERR CMD COMPLETE DATA NOT READY XXX NEXT CMD XXX ILLEGAL NEXT CMD NOT READY FILL LONG WRITE MEMORY LOCATION NEXT CMD NOT READY XXX NOT READY XXX BERR CMD COMPLETE MS DATA NOT READY NEXT CMD ...

Page 144: ...gister such as the PC or SR is altered by a BDM command while the processor is halted the updated value is used when prefetching resumes If a GO command is issued and the CPU is not halted the command is ignored Command Sequence Figure 5 30 GO Command Sequence Operand Data None Result Data The command complete response 0xFFFF is returned during the next shift operation 15 12 11 8 7 4 3 0 0x0 0xC 0...

Page 145: ...used as a null command where required Command Formats Command Sequence Figure 5 32 NOP Command Sequence Operand Data None Result Data The command complete response 0xFFFF with S cleared is returned during the next shift operation 15 12 11 8 7 4 3 0 0x0 0x0 0x0 0x0 Figure 5 31 NOP Command Format NOP NEXT CMD CMD COMPLETE ...

Page 146: ...nts are returned as a longword most significant word first The implemented portion of registers smaller than 32 bits is guaranteed correct other bits are undefined 15 12 11 8 7 4 3 0 Command 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D 31 16 D 15 0 Figure 5 33 RCREG Command Result Formats Table 5 19 Control Register Map Rc Register Definition Rc Register Definition 0x002 Cache control register ...

Page 147: ...h the operand data is to be written the second contains the data Result Data Successful write operations return 0xFFFF Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001 15 12 11 8 7 4 3 0 Command 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D 31 16 D 15 0 Figure 5 35 WCREG Command Result Formats EXT WORD NOT READY EXT WORD N...

Page 148: ... breakpoint has been enabled Command Result Formats Table 5 20 shows the definition of DRc encoding Command Sequence Figure 5 38 RDMREG Command Sequence Operand Data None Result Data The contents of the selected debug register are returned as a longword value The data is returned most significant word first 15 12 11 8 7 5 4 0 Command 0x2 0xD 100 DRc Result D 31 16 D 15 0 Figure 5 37 RDMREG BDM Com...

Page 149: ...time applications For these types of embedded systems the processor must continue to operate during debug The foundation of this area of debug support is that while the processor cannot be halted to allow debugging the system can generally tolerate small intrusions into the real time operation The debug module provides three types of breakpoints PC with mask operand address range and data with mas...

Page 150: ...causes the core to halt PST 0xF If the processor core cannot be halted the debug interrupt can be used With this configuration TDR TRC 10 the breakpoint trigger becomes a debug interrupt to the processor which is treated higher than the nonmaskable level 7 interrupt request As with all interrupts it is made pending until the processor reaches a sample point which occurs once per instruction Again ...

Page 151: ...ion processing It can be set while the processor is halted before reset exception processing begins See Section 5 5 1 CPU Halt A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when trace exception processing begins While operating in emulation mode the processor exhibits the follo...

Page 152: ...gn4 label2 bra w label2 The processor grants the internal bus if these loops are forced across two longwords 5 7 Processor Status DDATA Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction basis In general the PST DDATA output for an instruction is defined as follows PST 0x1 PST 0x89B DDATA ...

Page 153: ...e PST 0x8 DD destination bclr Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bra b w PST 0x5 bset imm ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bset Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bsr b w PST 0x5 PST 0xB DD destination operand btst imm ea x PST 0x1 PST 0x8 DD source operand btst Dy ea x PST 0x1 PST 0x8 DD source operand clr b ea x PST 0x1 PST 0x8 DD ...

Page 154: ...PST 0x1 move l ACC Rx PST 0x1 move l MACSR CCR PST 0x1 move l MACSR Rx PST 0x1 move l MASK Rx PST 0x1 move w ea y ea x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy imm CCR PST 0x1 movem l list ea x PST 0x1 PST 0xB DD destination 2 movem l ea y list PST 0x1 PST 0xB DD source 2 moveq imm Dx PST 0x1 msac l Ry Rx PST 0x1 msac l Ry Rx ea Rw PST 0x1 PST 0xB DD source ...

Page 155: ... ea y PST 0x4 PST 0x8 DD source operand wddata l ea y PST 0x4 PST 0xB DD source operand wddata w ea y PST 0x4 PST 0x9 DD source operand 1 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This includes the following ea x values An d16 An d8 An Xi d8 PC Xi 2 For Move Multiple instructions MOVEM...

Page 156: ...access to the user mode instructions plus the opcodes shown below The PST DDATA specification for these opcodes is shown in Table 5 23 The move to SR and RTE instructions include an optional PST 0x3 value indicating an entry into user mode Additionally if the execution of a RTE instruction returns the processor to emulator mode a multiple cycle status of 0xD is signaled Similar to the exception pr...

Page 157: ...x 13 Figure 5 41 Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved 1 GND GND RESET Pad Voltage2 GND PST2 PST0 DDATA2 DDATA0 Motorola reserved GND Core Voltage BKPT DSCLK Developer reserved 1 DSI DSO PST3 PST1 DDATA3 DDATA1 GND Motorola reserved PSTCLK 2Supplied by target 1Pins reserved for BDM developer use TEA ...

Page 158: ...5 46 MCF5272 User s Manual Motorola Recommended BDM Pinout ...

Page 159: ...the ColdFire core processor complex and the internal peripheral devices Figure 6 1 SIM Block Diagram SDRAM Controller External Bus Interface SYSTEM INTEGRATION MODULE SIM 32 Bit Address Bus 32 Bit Data Bus Interrupt Controller CS 7 0 8 8 8 4 ICRs MBAR PIWR CSORs CSBRs INT 6 1 6 DRAM Controller Outputs PIVR PITR ISR WRRR WIRR ALPR PMR System Control Base Address DIR Identification SDRAM Control SDC...

Page 160: ...Programmable wait states and port sizes Programmable address setup Programmable address hold for read and write SDRAM controller interface supported with CS7 SDCS See Chapter 8 Chip Select Module System protection Hardware watchdog timer See Section 6 2 3 System Configuration Register SCR Software watchdog timer See Section 6 2 8 Software Watchdog Timer Pin assignment register PAR configures the p...

Page 161: ...iguration register SCR p 6 5 System protection register SPR p 6 6 0x008 Power management register PMR p 6 7 0x00C Reserved Active low power register ALPR p 6 10 0x010 Device identification register DIR p 6 11 0x014 0x01C Reserved Interrupt Controller Registers 0x020 Interrupt control register 1 ICR1 p 7 4 0x024 Interrupt control register 2 ICR2 p 7 5 0x028 Interrupt control register 3 ICR3 p 7 5 0...

Page 162: ...eset All internal peripheral registers occupy a single relocatable memory block along 64 Kbyte boundaries If MBAR V is set MBAR BA is compared to the upper 16 bits of the full 32 bit internal address to determine if an internal peripheral is being accessed MBAR masks specific address spaces using the address space fields Attempts to access a masked address space generate an external bus access Add...

Page 163: ...ress range 3 SD Setting masks supervisor data space in MBAR address range 2 UC Setting masks user code space in MBAR address range 1 UD Setting masks user data space in MBAR address range 0 V Valid Determines whether MBAR settings are valid 0 MBAR contents are invalid 1 MBAR contents are valid 15 14 13 12 11 9 8 7 6 5 4 3 2 0 Field 1 0 RSTSRC Priority AR SoftRST BusLock HWR Reset 1 0 seeTable 6 3 ...

Page 164: ...higher priority than other requesting masters but is not requesting the bus for the next cycle there is a 1 clock dead cycle before the arbiter can reassign the bus to the next highest priority master 6 SoftRST Writing a one to this bit resets the on chip peripherals excluding the chip select module interrupt controller module GPIO module and SDRAM controller and asserts RSTO The CPU is not reset ...

Page 165: ...ion This bit is set when an access is attempted to an on chip peripheral whose clock has been stopped If SMVEN is also set the bus cycle is terminated with an access error exception 12 4 PE PEEN Peripheral error This bit is set when an access to an on chip peripheral is terminated with a transfer error If PEEN is also set the bus cycle is terminated with an access error exception 11 3 HWT HWTEN Ha...

Page 166: ...riptions Bits Field Description 31 BDMPDN Debug power down enable Controls the clocking to the debug module 0 Clock enabled 1 Clock disabled 30 27 Reserved should be cleared 26 ENETPDN Ethernet power down enable Controls the clocking to the ethernet module 0 Clock enabled 1 Clock disabled 25 PLIPDN PLIC power down enable Controls the clocking to the PLIC module 0 Clock enabled 1 Clock disabled 24 ...

Page 167: ...ge in signal level is detected on USD_D or INT1 USB_WOR See Table 6 6 for a description of the interaction between the PDN and WK bits 0 Wakeup disabled 1 Wakeup enabled USBPDN must also be set 9 UART1WK UART1 wakeup enable Allows clocking to the UART1 module to be restored when a change in signal level is detected on UART1RxD See Table 6 6 for a description of the interaction between the PDN and ...

Page 168: ...ch internal clocking to the CPU is disabled To enter sleep mode the user must write to the ALPR and then execute a STOP instruction See Section 6 2 6 Activate Low Power Register ALPR Individual modules may have clocking disabled through the appropriate PDN bits After SLPEN is set a write access must be made to ALPR to actually enter sleep mode D 31 0 are driven low and other bus signals are negate...

Page 169: ...pt request from an external device as detailed in Table 6 7 6 2 7 Device Identification Register DIR The DIR Figure 6 7 contains a value representing the identification mark for the MCF5272 device This register contains the same value as the JTAG IDCODE register The version number field will change if a new revision of the MCF5272 is created Table 6 7 Exiting Sleep and Stop Modes Interrupt Source ...

Page 170: ...set timeout value WER WIE is set and a maskable interrupt is issued at the level defined by ICR4 SWTOIPL The software watchdog consists of a 16 bit counter with a 10 bit prescaler It counts up to a maximum of 65536 with a resolution of 32768 clock periods Thus at 66 MHz the resolution of the watchdog is 0 5 msec with a maximum timeout period of 32768 65536 231 clock periods or 32 54 S Timeout WRRR...

Page 171: ...erence value This field determines the reset timeout value Reset initializes this register to 0xFFFE disabling the watchdog timer and setting it to the maximum timeout value 0 EN Enable watchdog When enabled software should periodically write to WCR to avoid reaching the reset reference value 0 Watchdog timer disabled 1 Watchdog timer enabled 15 1 0 Field REF IEN Reset 1111_1111_1111_1110 R W R W ...

Page 172: ...ield COUNT Reset 0000_0000_0000_0000 R W R W Address MBAR 0x288 Figure 6 10 Watchdog Counter Register WCR 15 1 0 Field WIE Reset 0000_0000_0000_0000 R W R W Address MBAR 0x28C Figure 6 11 Watchdog Event Register WER Table 6 11 WER Field Descriptions Bits Field Description 15 1 Reserved should be cleared 0 WIE Watchdog interrupt event 0 WIRR value has not been reached 1 WIRR value has been reached ...

Page 173: ...isters in the interrupt controller memory map and the interrupt priority scheme 7 1 Overview The SIM provides a centralized interrupt controller for all MCF5272 interrupt sources which consist of the following External interrupts INT 6 1 Timer modules UART modules PLIC module USB module DMA module Ethernet module QSPI module Software watchdog timer SWT Figure 7 1 is a block diagram of the interrup...

Page 174: ...h interrupt sources can reactivate the CPU from low power sleep or stop mode The programmable interrupt vector register PIVR specifies which vector number is returned in response to an interrupt acknowledge cycle 7 2 Interrupt Controller Registers The interrupt controller register portion of the SIM memory map is shown in Table 7 1 Table 7 1 Interrupt Controller Registers MBAR Offset 31 24 23 16 1...

Page 175: ...d system stack should be set up before this initialization If more than one interrupt source has the same interrupt priority level IPL the interrupt controller daisy chains the interrupts with the priority order following the bit placement in the PIWR with INT1 having the highest priority and SWTO having the lowest priority as shown in Figure 7 8 7 2 1 Interrupt Controller Registers This section d...

Page 176: ... bit is to be left unchanged 7 2 2 1 Interrupt Control Register 1 ICR1 ICR1 Figure 7 2 is used to configure interrupts from various on and off chip sources Table 7 3 describes ICR1 fields ETx Ethernet module transmit data interrupt ERx Ethernet module receive data interrupt ENTC Ethernet module non time critical interrupt QSPI Queued serial peripheral interface IPL2 IPL1 IPL0 Interrupt priority le...

Page 177: ...urces this bit is cleared when the interrupt is cleared in the module registers 0 No interrupt pending 1 An interrupt is pending 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 IPL Interrupt priority level Specifies the IPL for the corresponding interrupt source This field can be changed only when a 1 is simultaneously written to the corresponding PI bit 000 The corresponding INT source is inhibited an...

Page 178: ...s give the value of the interrupt source prior to input synchronization or polarity correction 31 30 28 27 26 24 23 22 20 19 18 16 Field USB4PI USB41IPL USB5PI USB5IPL USB6PI USB6IPL USB7PI USB7IPL Reset 0000_0000_0000_0000 15 14 12 11 10 8 7 6 4 3 2 0 Field DMAPI DMAIPL ERXPI ERXIPL ETXPI ETXIPL ENTCPI ENTCIPL Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x028 Figure 7 4 Interrupt Control Register...

Page 179: ...d INT1 INT2 INT3 INT4 TMR1 TMR2 TMR3 TMR4 Reset XXXX_1111 R W Read only 23 22 21 20 19 18 17 16 Field UART1 UART2 PLI_P PLI_A USB0 USB1 USB2 USB3 Reset 1111_1111 R W Read only 15 14 13 12 11 10 9 8 Field USB4 USB5 USB6 USB7 DMA ERx ETx ENTC Reset 1111_1111 R W Read only 7 6 5 4 3 0 Field QSPI INT5 INT6 SWTO Reset 1XX1_0000 R W Read only Address MBAR 0x030 Figure 7 6 Interrupt Source Register ISR T...

Page 180: ...ity level IPL programmed in the ICRs the interrupt controller daisy chains the interrupts with the priority order following the bit placement in the PIWR with INT1 having the highest priority and SWTO having the lowest priority as shown in Figure 7 8 31 30 29 28 27 16 Field INT1 INT2 INT3 INT4 Reset 0000_0000_0000_0000 15 7 6 5 4 0 Field INT5 INT6 Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x034 ...

Page 181: ... priority interrupt that is being acknowledged and provide the interrupt vector to the core The three most significant bits of the interrupt vector are programmed by the user in the PIVR The lower five bits are provided by the interrupt controller depending on the source as shown in Table 7 7 31 30 29 28 27 26 25 24 Field INT1 INT2 INT3 INT4 TMR1 TMR2 TMR3 TMR4 Reset 1111_1111 R W R W 23 22 21 20 ...

Page 182: ...r numbers shown assume PIVR IV 0b010 If another value of PIVR IV is used the vector numbers would change accordingly 7 5 4 0 Field IV Reset 0000_1111 R W R W Address MBAR 0x03F Table 7 7 PIVR Field Descriptions Bits Field Description 7 5 IV These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all sources To conform to the core interrupt vector alloca...

Page 183: ... 10100 USB7 USB Endpoint 7 85 10101 DMA DMA Controller 86 10110 ERx Ethernet Receiver 87 10111 ETx Ethernet Transmitter 88 11000 ENTC Ethernet Module Non time critical 89 11001 QSPI Queued Serial Peripheral Interface 90 11010 INT5 External Interrupt Input 5 91 11011 INT6 External Interrupt Input 6 92 11100 SWTO Software Watchdog Timer Timeout 93 11101 Reserved Reserved 94 11110 Reserved Reserved 9...

Page 184: ...7 12 MCF5272 User s Manual Interrupt Controller Registers ...

Page 185: ...mmable chip selects Address masking for memory block sizes from 4 Kbytes to 2 Gbytes Programmable wait states and port sizes Programmable address setup Programmable address hold for read and write SDRAM controller interface supported with CS7 SDCS Global chip select functionality 8 1 2 Chip Select Usage Each of the eight chip selects CS0 CS7 is configurable for external SRAM ROM and peripherals CS...

Page 186: ...dditional setup hold extended burst capability wait states and read write access Table 8 1 CSCR and CSOR Values after Reset Offset Name Chip Select Register Reset 0x040 CSBR0 CS base register 0 0x0000_0x011 1 The nibble shown as x resets as 00xx where the undefined bits represent the BW field QSPI_CS0 BUSW0 and QSPI_CLK BUSW1 program the bus width for CS0 at reset 0x044 CSOR0 CS option register 0 ...

Page 187: ...ropriate bus interface module onto the device pins 00 16 32 bit SRAM ROM For 16 32 bit wide memory devices with byte strobe inputs CSBR0 EBI 00 at reset Affects all chip selects 01 SDRAM One physical bank of SDRAM consisting of 16 256 Mbit devices CSOR7 WS must be set to 0x1F Affects only CS7 SDCS 10 Reserved 11 Use SRAM ROM timing for 8 bit devices without byte strobe inputs 9 8 BW Bus width Dete...

Page 188: ...11 100 Interrupt acknowledge level 4 11 101 Interrupt acknowledge level 5 11 110 Interrupt acknowledge level 6 11 111 Interrupt acknowledge level 7 1 CTM Compare TM Enables comparison between the access type and the TM and TT bits 0 TT and TM register bits do not affect address match 1 TT and TM register bits must match the access type for an address match to occur 0 ENABLE Enable Disables enables...

Page 189: ...Address mask Masks equivalent CSOR BA bits The BAM setting chooses which BA bits to compare with the corresponding address bit to determine a match 0 Mask address bit 1 Compare address bit 11 ASET Address setup enable Controls assertion of chip select with respect to assertion of a valid address that hits in the chip select address space 0 Assert chip select on the rising edge of CLK that address ...

Page 190: ...es 0x01 1 wait state 0x1E 30 wait states 0x1F External access For example WS 0x0A introduces a 10 clock wait before the bus cycle terminates 0x1F indicates a source external to the chip select module terminates the access For SRAM and ROM accesses EBI codes 00 or 11 and WS 0x1F TA must be driven from an external source to terminate the bus cycle otherwise the on chip bus timeout monitor issues a b...

Page 191: ...ide pin out compatibility for different SDRAM sizes with a single printed circuit board layout Page size from 256 1024 column address locations 6 1 1 1 timing for burst read 3 1 1 1 timing for burst write accesses assuming a page hit at 66 MHz CAS latencies of 1 and 2 Up to four concurrently activated banks SDRAM power down and self refresh Refresh timer prescaler supports system clock down to 5 M...

Page 192: ...tput DRESETEN DRESETEN is asserted to indicate that the SDRAM controller is to be reset whenever RSTI asserts If DRESETEN is negated RSTI does not affect the SDRAM controller which continues to refresh external memory This is useful for debug situations where a reset of the device is required without losing data located in SDRAM DRESETEN is normally tied high or low depending on system requirement...

Page 193: ...is allows using SDRAM devices of different sizes without changing the board layout See Table 9 7 SDCLK SDRAM bus clock same frequency as CPU clock This dedicated output reduces setup and hold time uncertainty due to process and temperature variations SDCLK is disabled for SDRAM power down mode SDCLKE SDRAM clock enable SDRAMCS CS7 SDRAM chip select CS7 The SDRAM is assigned to CS7 SDRAMCS of the d...

Page 194: ...VDD GND DQ15 GND DQ14 DQ13 VDD DQ12 DQ11 GND DQ10 DQ9 VDD DQ8 GND NC DQMH CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VDD DQ0 VDD DQ1 DQ2 GND DQ3 DQ4 VDD DQ5 DQ6 GND DQ7 VDD DQML R W CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDD DQ1 DQ2 GND DQ3 DQ4...

Page 195: ...Kbytes 512 Kbytes 1 Kbyte 1 Kbyte Number of banks 2 4 2 4 4 4 Refresh count in 64 mS 4K 4K 4K 4K 4K 8K Table 9 4 Configurations for 32 Bit Data Bus Parameter 8 Bit 16 Bit 32 Bit 16 Mbyte 64Mbyte 16 Mbyte 64 Mbyte 128 Mbyte 256 Mbyte 64 Mbyte 128 Mbyte Number of devices 4 2 1 Total size 8 Mbytes 32 Mbytes 4 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes 8 Mbytes 16 Mbytes Total page size 2 Kbytes 2 Kbytes 1 ...

Page 196: ... 16 Mbytes 64 Mbytes 16 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 64 Mbytes 128 Mbytes A2 A0 A2 A11 A2 A11 A2 A10 A2 A10 A2 A11 A2 A11 A2 A10 A2 A10 A3 A1 A3 A12 A3 A12 A3 A11 A3 A11 A3 A12 A3 A12 A3 A11 A3 A11 A4 A2 A4 A13 A4 A13 A4 A12 A4 A12 A4 A13 A4 A13 A4 A12 A4 A12 A5 A3 A5 A14 A5 A14 A5 A13 A5 A13 A5 A14 A5 A14 A5 A13 A5 A13 A6 A4 A6 A15 A6 A15 A6 A14 A6 A14 A6 A15 A6 A15 A6 A14 A6 A14 A7 A5 ...

Page 197: ...n page only the READ or WRITE command is issued to the SDRAM This is called a page hit In two page SDRAMs banks 2 and 3 are invalid and must not be addressed To avoid address aliasing the user should restrict the chip select address range to the space available in the SDRAMs 9 5 SDRAM Registers The SDRAM configuration register SDCR and the SDRAM timing register SDTR are described in the following ...

Page 198: ...mode for read data access It forces the SDRAM controller to register the read data adding one wait state to single read accesses and to the first word read during a burst REG must be 1 for clock frequencies above 48 MHz to meet input setup timing for data input See electrical characteristics timing SD16 The description of INV shows how REG and INV interact 3 INV Invert clock Inverts SDRAM clock ou...

Page 199: ...ns Bits Name Description 15 10 RTP Refresh timer prescaler Determines the number of clock cycles x 16 between refreshes The following table describes different recommended prescaler settings for different clock frequencies including a margin of 1 2 µS Recommended values are as follows RTP 15 6 µs 1 f RTP 16 System Clock 111101 61 66 MHz 101011 43 48 MHz 011101 29 33 MHz 010110 22 25 MHz 000100 4 5...

Page 200: ...d by SDTR CLT SDCR ACT is set after initialization 9 7 Power Down and Self Refresh The SDRAM can be powered down by setting SDCR GSL The SDRAM controller executes the required power down command sequence to ensure self refresh during power down The SDRAM controller completes the current memory access then automatically issues the following commands to force the SDRAM into sleep mode PRECHARGE ALL ...

Page 201: ...PC100 compliant SDRAM device at 66 MHz Page miss latency includes the cycles to precharge the last open page and activate the new page before the read write access There are no precharge cycles when an address hits an open page In Table 9 9 the timing configuration is RTP 61 RC negligible RCD 0 or 1 RP 1 or 0 and CLT 1 In Table 9 10 the timing configuration is RTP 61 RC negligible RCD 0 RP 0 and C...

Page 202: ...eat read Page miss 9 10 Page hit 5 6 Single beat longword read Page miss 9 1 10 1 Page hit 5 1 6 1 Single beat write Page miss 7 7 Page hit 3 3 Single beat longword write Page miss 7 1 7 1 Page hit 3 1 3 1 Burst read Page miss 9 1 1 1 1 1 1 1 16 10 1 1 1 1 1 1 1 17 Page hit 5 1 1 1 1 1 1 1 12 6 1 1 1 1 1 1 1 13 Burst write Page miss 7 1 1 1 1 1 1 1 14 7 1 1 1 1 1 1 1 14 Page hit 3 1 1 1 1 1 1 1 10...

Page 203: ...1 16 Page hit 5 1 1 1 1 1 1 1 12 6 1 1 1 1 1 1 1 13 Burst write Page miss 6 1 1 1 1 1 1 1 13 6 1 1 1 1 1 1 1 13 Page hit 3 1 1 1 1 1 1 1 10 3 1 1 1 1 1 1 1 10 Table 9 13 SDRAM Controller Performance 16 Bit Port RCD 0 RP 0 SDRAM Access Number of System Clock Cycles REG 0 INV 0 REG 1 INV 0 Single beat read Page miss 7 8 Page hit 5 6 Single beat longword read Page miss 7 1 8 1 Page hit 5 1 6 1 Single...

Page 204: ...aining data and control signals can be refined by setting SDCR INV which inverts the SDRAM clock SDCR REG must always be cleared when SDCR INV is set Figure 9 6 Timing Refinement with Inverted SDCLK NOTE If the delay difference between the fastest data signal and the slowest control signal exceeds half of the clock cycle time the clock shift can cause hold time violations on control signals The in...

Page 205: ...ead access time reduces effective CAS latency by 1 cycle Figure 9 8 Timing Refinement with Effective CAS Latency NOTE When reduced effective CAS latency is used the SDRAM is still programmed with true CAS latency The SDRAM controller state machine must be reprogrammed for the reduced CAS latency SDRAM initialization software Shifted delay of SDCLK Delay SDCLK to CLK SDRAM read access time TSDCLK_t...

Page 206: ...d CSOR7 WAITST should be programmed for 0x1F to ensure that the internal bus cycle termination signal is sourced from the SDRAM controller and not the chip select module NOTE The SDRAM shares address and data signals with external memory and peripherals Due to stringent SDRAM timing requirements it is strongly recommended to buffer the address byte strobe and data buses between the MCF5272 and non...

Page 207: ...hut off by putting the SDRAM controller into power down or self refresh mode 9 10 1 SDRAM Read Accesses The read examples Figure 9 9 and Figure 9 10 show a CAS latency of 2 SDCR REG 0 and SDCR INV 1 In T1 the ColdFire core issues the address This cycle is internal to the device and always occurs In T2 the SDRAM controller determines if there is a page miss or hit This cycle is internal to the devi...

Page 208: ...lock cycle T2 to determine whether the access is a hit or a miss Because it is a hit the burst operation follows immediately Col T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Data Data Data Data Row Col Col Col Row Bank x Bank y Bank y SDCLK SDCLKE SDADR 13 0 10_PRECHG SDBA 1 0 SDCS RAS0 CAS0 SDWE BS 3 0 D 31 0 Issue Address Page Hit or Miss Precharge Old Page Activate New Page CF2 Core 1 Read 2 R...

Page 209: ... access is page hit or miss In the burst write page miss example shown in Figure 9 11 after the SDRAM determines that this is a page miss T2 the precharge old page T3 and activate new page cycles T5 are required Cycle T6 is a wait state for SDRAM activation command as it is in Figure 9 9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Data Data Data Data Col Col Col Col Bank SDCLK SDCLKE SDADR 13 0 A10_PRECHG SDBA ...

Page 210: ...AM controller determines that the access is a page hit in T2 the burst transfer begins in T3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T1 Data Data Data Data Row Col Col Col Col Row Bank x Bank y Bank y SDCLK SDCLKE SDADR 13 0 A10_PRECHG SDBA 1 0 SDCS RAS0 CAS0 SDWE BS 3 0 D 31 0 Issue Address Page Hit or Miss Precharge Old Page Activate New Page CF2 Core Write 1 Write 2 Write 4 Write 3 ...

Page 211: ...AM writes all of its on chip RAM page buffers into the SDRAM array SDTR RP determines the number of dead cycles after a precharge Note that self refresh occurs during T3 In refresh state SDRAM cannot accept any other command T0 T1 T2 T3 T4 T5 T6 T7 T8 Data Data Data Data Col Col Col Col Bank SDCLK SDCLKE SDADR 13 0 A10_PRECHG SDBA 1 0 SDCS RAS0 SDWE BS 3 0 D 31 0 Issue Address Page Hit or Miss CF2...

Page 212: ...uffers back into the SDRAM array The SDTR RP value determines the number of dead cycles after a precharge Note that auto refresh occurs in T3 SDTR RC determines the number of clock cycles the SDRAM remains in refresh state during which time it cannot accept other commands T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 SDCLK SDADR 13 0 A10_PRECHG SDBA 1 0 SDCS RAS0 SDWE Precharge All Banks NOP Auto Refresh CAS0 SDC...

Page 213: ...h mode Note that SDCR GSL is sampled on the rising edge of the internal clock If it is 0 as it is here SDRAM controller signals become active on the following negative clock edge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Internal Clock SDCLK SDADR 13 0 A10_PRECHG SDBA 1 0 SDCS RAS0 SDWE Precharge All BanksNOP Self Refresh CAS0 SDCR SLEEP SDCLKE ...

Page 214: ...s Manual SDRAM Interface Figure 9 15 Exit SDRAM Self Refresh Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 Internal Clock SDCLK SDADR 13 0 SDBA 1 0 SDCS RAS0 SDWE NOP CAS0 SDCR GSL SDCLKE NOP NOP NOP NOP NOP NOP SDCR SLEEP A10_PRECHG ...

Page 215: ...rnal SRAM or on chip peripheral in any combination NOTE Memory to memory DMA transfers run to completion if the assume request bit in the system configuration register SCR AR is set This generally prevents the CPU from recognizing interrupts and blocks bus accesses by other on chip bus masters It is best not to enable SCR AR when the DMA controller is in use When AR 0 the DMA controller allows the...

Page 216: ...r by the number of bytes transferred This mode should be used when a source or destination address is in external memory 10 3 DMA Controller Registers The MCF5272 DMA controller supports a single DMA channel which can be used for memory to memory transfers 10 3 1 DMA Mode Register DMR The DMR controls various operation modes principally the request and addressing modes Fields include the transfer ...

Page 217: ...tion addressing mode for the channel 00 Static address mode 01 Increment address mode 1x Reserved do not use 12 10 DSTT Destination addressing type Used internal to the MCF5272 to qualify the address bits This value should be compatible with the CSCRn TM value used for external RAM or peripheral device access 000 Reserved 001 User data access 010 User code access 011 100 Reserved 101 Supervisor da...

Page 218: ...tination data write of the size programmed in DSTS the data is written to the destination address Thus source accesses can be longword type and destination addresses can be line burst type In this case 4 longword reads are performed followed by an indivisible burst write of 4 longwords The most efficient data transfer method is to use longword or line burst transfer types SRCS Data Transfer Type A...

Page 219: ...s not complete 1 The address sequence is complete This occurs when the byte counter decrements to 0 Corresponds to DMA complete ASC remains set until it is cleared by writing a 1 to its location or by a hardware reset Writing a 0 has no effect No further transfers can take place when ASC is set It is important to ensure that the combination of source address destination address and transfer sizes ...

Page 220: ... by the number of bytes transferred DIR ASC is set when the byte counter reaches zero The user must ensure that the bytes remaining to be transferred and the transfer size are such that the byte counter decrements to zero or wraps around without setting the ASC flag 31 0 Field SRCADR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R W R W Addr MBAR 0x00EC Figure 10 3 DMA Source Address Register DSAR...

Page 221: ...net controller FEC incorporates the following features Full compliance with the IEEE 802 3 standard Support for three different physical interfaces 100 Mbps 802 3 media independent interface MII 10 Mbps 802 3 MII 10 Mbps seven wire interface Half duplex 100 Mbps operation at system clock frequency 50 MHz 448 bytes total on chip transmit and receive FIFO memory to support a range of bus latencies N...

Page 222: ... is divided into three sections transmit FIFO receive FIFO and descriptor controller memory User data flows to or from the DMA unit from or to the receive transmit FIFOs Transmit data flows from the transmit FIFO into the transmit block Receive data flows from the receive block into the receive FIFO The user controls the FEC by writing into control registers located in each block The control and s...

Page 223: ...l interface for 10 Mbps Ethernet The interface mode is selected by R_CNTRL MII_MODE In MII mode the 802 3 standard defines and the FEC module supports 18 signals These are shown in Table 11 1 The serial mode interface operates in what is generally referred to as AMD mode The MCF5272 configuration for seven wire serial mode connections to the external transceiver are shown in Table 11 2 Table 11 1 ...

Page 224: ...active the controller waits to verify that it stays inactive for 60 bit times If so the transmission begins after waiting an additional 36 bit times 96 bit times after carrier sense originally went inactive If a collision occurs during the transmit frame the FEC follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached The FEC stores the first 6...

Page 225: ...gister settings Setting the graceful transmit stop bit X_CNTRL GTS pauses transmission The FEC transmitter stops immediately if no transmission is in progress Otherwise it continues transmission until the current frame finishes normally or terminates with a collision When X_CNTRL GTS is cleared the FEC resumes transmission with the next frame The FEC transmits bytes lsb first 11 4 1 FEC Frame Rece...

Page 226: ...table and if it is empty continues transferring the rest of the frame to this BD s associated data buffer The RxBD length is determined in the R_BUFF_SIZE value in the R_BUFF_SIZE register The user should program R_BUFF_SIZE to be at least 128 bytes R_BUFF_SIZE must be quad word 16 byte aligned During reception the FEC checks for a frame that is either too short or too long When the frame ends car...

Page 227: ...ives all of the incoming frames regardless of their address In this mode the destination address lookup is still performed and RxBD MISS is set accordingly If address recognition did not achieve a match the frame is received with RxBD MISS set If address recognition achieves a match the frame is received without setting RxBD MISS Destination Address Type FEC Address Processing individual The FEC c...

Page 228: ...lects HASH_TABLE_HIGH bit 31 1 or HASH_TABLE_LOW bit 31 0 Bits 30 26 of the CRC result select the bit within the selected register If the CRC generator selects a bit that is set in the hash table the frame is accepted otherwise it is rejected The result is that if eight group addresses are stored in the hash table and random group addresses are received the hash table prevents roughly 56 64 or 87 ...

Page 229: ...ing frame may be discarded by the receiver 11 4 6 Collision Handling If a collision occurs during transmission the FEC continues transmitting for at least 32 bit times sending a JAM pattern of 32 ones The JAM pattern follows the preamble sequence if the collision occurs during preamble If a collision occurs within 64 byte times the retry process is initiated The transmitter waits a random number o...

Page 230: ... closed with the LC bit set in the last TxBD for that frame The FEC then continues to the next TxBD and begins sending the next frame Heartbeat Some transceivers have a self test feature called heartbeat or signal quality error To signify a good self test the transceiver indicates a collision within 20 clocks after the FEC sends a frame This heartbeat condition does not imply a real collision but ...

Page 231: ...4 0x84C IVEC 32 Interrupt vector status register p 11 15 0x850 R_DES_ACTIVE 32 Receive descriptor active register p 11 16 0x854 X_DES_ACTIVE 32 Transmit descriptor active register p 11 17 0x880 MII_DATA 32 MII management frame register p 11 17 0x884 MII_SPEED 32 MII speed control register p 11 19 0x8CC R_BOUND 32 FIFO receive bound register p 11 20 0x8D0 R_FSTART 32 FIFO receive start register p 1...

Page 232: ...0_0000_0000_0000 R W Read write 15 2 1 0 Field ETHER_EN RESET Reset 0000_0000_0000_0000 R W Read write Addr MBAR 0x840 Figure 11 5 Ethernet Control Register ECNTRL Table 11 7 ECNTRL Field Descriptions Bits Name Description 31 26 Reserved should be cleared 25 TX_RT Transmit retime 0 Normal operation seven wire serial mode 1 The transmit output signals E_TxD 3 0 E_TxEN and E_TxER are delayed by one ...

Page 233: ...s automatically cleared by hardware once the reset sequence is complete approximately 16 clock cycles after being set 31 30 29 28 27 26 25 24 23 22 21 20 16 Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR UMINT Reset 0000_0000_0000_0000 R W Read write 15 0 Field Reset 0000_0000_0000_0000 R W Read write Addr MBAR 0x844 Table 11 8 I_EVENT Field Descriptions Bits Name Description 31 HBERR Heartbe...

Page 234: ...nterrupt status An interrupt is currently being asserted to the interrupt controller This bit is not maskable 20 0 Reserved should be cleared 31 30 29 28 27 26 25 24 23 22 21 16 Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR Reset 0000_0000_0000_0000 R W Read write 15 0 Field Reset 0000_0000_0000_0000 R W Read write Addr MBAR 0x848 Figure 11 6 I_MASK Register Table 11 9 I_MASK Register Field ...

Page 235: ... receive descriptor whose E bit is not set it clears the R_DES_ACTIVE bit and stops polling the receive descriptor ring The R_DES_ACTIVE register is cleared at reset and when ETHER_EN is cleared 31 16 Field Reset 0000_0000_0000_0000 R W Read Only 15 4 3 2 1 0 Field IVEC Reset 0000_0000_0000_0000 R W Read Only Addr MBAR 0x84C Figure 11 7 Interrupt Vector Status Register IVEC Table 11 10 IVEC Field ...

Page 236: ...ansmit frames provided ETHER_EN is also set As soon as the FEC polls a transmit descriptor whose ready bit is not set it clears the X_DES_ACTIVE bit and stops polling the transmit descriptor ring The X_DES_ACTIVE register is cleared at reset and when ETHER_EN is cleared Figure 11 9 describes this register 31 25 24 23 16 Field R_DES_ACTIVE Reset 0000_0000_0000_0000 R W Read Write 15 0 Field Reset 0...

Page 237: ...y written to MII_DATA This allows MII_DATA and MII_SPEED to be programmed in either order if MII_SPEED is currently zero 31 25 24 23 16 Field X_DES_ACTIVE Reset 0000_0000_0000_0000 R W Read Write 15 0 Field Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x854 Figure 11 9 X_DES_ACTIVE Register Table 11 12 X_DES_ACTIVE Field Descriptions Bits Name Description 31 25 Reserved should be cleared 24 ...

Page 238: ...X to MII_DATA the contents of the DATA field are a don t care Writing this pattern causes the control logic to shift out the data in the MII_DATA register following a preamble generated by the control state machine The contents of the MII_DATA register are altered as the contents are serially shifted and are unpredictable if read by the user Once the read management frame operation completes the M...

Page 239: ...g either a rising or falling edge of E_MDC If the system clock is 50 MHz programming this register to 0x0000_000A results in an E_MDC frequency of 25 MHz 1 10 2 5 MHz Table 11 15 shows optimum values for 31 16 Field Reset 0000_0000_0000_0000 R W Read Write 15 8 7 6 1 0 Field DIS_PREAMBLE MII_SPEED Reset 0000_0000 0 000_000 0 R W Read Write Addr MBAR 0x884 Figure 11 11 MII Speed Control Register MI...

Page 240: ..._FSTART The R_FSTART register Figure 11 13 is programmed by the user to indicate the starting address of the receive FIFO R_FSTART marks the boundary between the transmit and Table 11 15 Programming Examples for MII_SPEED Register System Clock Frequency MII_SPEED E_MDC frequency 25 MHz 0x3 2 08 MHz 33 MHz 0x4 2 06 MHz 50 MHz 0x5 2 5 MHz 66 MHz 0x7 2 36 MHz 31 16 Field Reset 0000_0000_0000_0000 R W...

Page 241: ... amount of data required in the transmit FIFO before transmission of a frame can begin Setting X_WMRK to larger values reduces the risk of transmit FIFO underrun due to system bus latency 31 16 Field Reset 0000_0000_0000_0000 R W Read Write 15 11 10 9 2 1 0 Field 1 R START Reset 0000_0 1 01_0000_00 00 R W Read Write Addr MBAR 0x8D0 Figure 11 13 FIFO Receive Start Register R_FSTART Table 11 17 R_FS...

Page 242: ...eset to the first available RAM address 31 16 Field Reset 0000_0000_0000_0000 R W Read Write 15 2 1 0 Field X_WMRK Reset 0000_0000_0000_00 00 R W Read Write Addr MBAR 0x8E4 Figure 11 14 Transmit FIFO Watermark X_WMRK Table 11 18 X_WMRK Field Descriptions Bits Name Description 31 2 Reserved should be cleared 1 0 X_WMRK Transmit FIFO watermark Frame transmission begins when the number of bytes selec...

Page 243: ...RT Reset 0000_0 1 0001_1000 00 R W Read Write Addr MBAR 0x8EC Figure 11 15 FIFO Transmit Start Register X_FSTART Table 11 19 X_FSTART Field Descriptions Bits Name Description 31 11 Reserved should be cleared 10 Reserved should be set 9 2 X_FSTART Transmit FIFO starting address Address of first transmit FIFO location 1 0 Reserved should be cleared 31 16 Field Reset 0000_0000_0000_0000 R W Read Writ...

Page 244: ...mes are accepted regardless of address matching 2 MII_MODE MII mode enable Selects the external interface mode Setting this bit to one selects MII mode setting this bit equal to zero selects seven wire mode used only for serial 10 Mbps This bit controls the interface mode for both transmit and receive blocks 1 DRT Disable receive on transmit 0 Receive path operates independently of transmit use fo...

Page 245: ...f the CRC register 23 11 Reserved should be cleared 10 0 MAX_FL Maximum frame length Length is measured starting at DA and includes the CRC at the end of the frame Transmit frames longer than MAX_FL cause the BABT interrupt to occur Receive frames longer than MAX_FL cause the BABR interrupt to occur and set the LG bit in the end of frame buffer descriptor Frames exceeding the MAX_FL are not trunca...

Page 246: ...window This bit should be modified only when ETHER_EN is deasserted 0 GTS Graceful transmit stop When this bit is set the MAC stops transmission after any current frame is complete and the GRA interrupt in the INTR_EVENT register is asserted If frame transmission is not currently underway the GRA interrupt is asserted immediately Once transmission is complete a restart is accomplished by clearing ...

Page 247: ...tialized by the user prior to operation 31 16 Field ADDR_HIGH Reset Undefined R W Read Write 15 0 Field ADDR_HIGH Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0xC04 Figure 11 20 RAM Perfect Match Address High ADDR_HIGH Table 11 24 ADDR_HIGH Field Descriptions Bits Name Description 31 0 ADDR_HIGH Bytes 4 bits 31 24 and 5 bits 23 16 of the 6 byte address 31 16 Field HASH_HIGH Reset Undefined R...

Page 248: ...ser Non zero values in these two bit positions are ignored by the hardware Table 11 25 HASH_TABLE_HIGH Field Descriptions Bits Name Description 31 0 HASH_HIGH The HASH_TABLE_HIGH register contains the upper 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a multicast address Bit 31 of HASH_TABLE_HIGH contains hash index bit 63 Bit 0 of HASH_TABLE_HIG...

Page 249: ... user Non zero values in these two bit positions are ignored by the hardware This register is not reset and must be initialized by the user prior to operation 31 16 Field R_DES_START Reset Undefined R W Read Write 15 2 1 0 Field R_DES_START 0 0 Reset Undefined R W Read Write Addr MBAR 0xC10 Figure 11 23 Pointer to Receive Descriptor Ring R_DES_START Table 11 27 R_DES_START Field Descriptions Bits ...

Page 250: ...bytes This register Figure 11 25 is not reset and must be initialized by the user prior to operation 11 5 22 Initialization Sequence This section describes which registers and RAM locations are reset due to hardware reset which are reset due to the FEC reset and what locations the user must initialize before enabling the FEC Table 11 28 X_DES_START Field Descriptions Bits Name Description 31 2 X_D...

Page 251: ... a bad CRC is sent as shown in Table 11 31 11 5 23 User Initialization Prior to Asserting ETHER_EN The user must initialize portions the FEC prior to setting the ETHER_EN bit The exact values depend on the particular application The sequence is similar to the procedure defined in Table 11 32 Table 11 30 Hardware Initialization User System Register Machine Reset Value User ECNTRL Cleared I_EVENT Cl...

Page 252: ...r initializes portions of the FEC after setting ETHER_EN The exact values depend on the particular application The sequence probably resembles the steps shown in Table 11 33 though these could also be done before asserting ETHER_EN 3 Set IVEC define ILEVEL 4 Set R_FSTART optional 5 Set X_FSTART optional 6 Set ADDR_HIGH and ADDR_LOW 7 Set HASH_TABLE_HIGH and HASH_TABLE_LOW 8 Set R_BUFF_SIZE 9 Set R...

Page 253: ... external memory for the transmit or receive data traffic respectively The hardware reads the BDs and processes the buffers after they have been defined After the data DMA is complete and the BDs have been written by the DMA engine RxBD E or TxBD R are cleared by hardware to indicate that the buffer has been processed Software may poll the BDs to detect when the buffers have been processed or may ...

Page 254: ... will modify the E L M LG NO SH CR and OV bits and write the length of the used portion of the buffer in the first word The M LG NO SH CR and OV bits in the first word of the buffer descriptor are modified by the FEC only when the L bit is set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 E RO1 W RO2 L M BC MC LG NO SH CR OV TR 2 DATA LENGTH 4 Rx Data Buffer Pointer A 31 16 6 Rx Data Buffer Pointer A 15...

Page 255: ... the M bit to quickly determine whether the frame was destined to this station Valid only if the L bit and the PROM bit are set 0 The frame was received because of an address recognition hit 1 The frame was received because of promiscuous mode 7 BC Broadcast Written by the FEC Will be set if DA is broadcast FF FF FF FF FF FF 6 MC Mulitcast Written by the FEC Is set if DA is multicast and not BC 5 ...

Page 256: ...nd will modify the DEF HB LC RL RC UN and CSL status bits in the first word of the BD after the buffer is sent as a DMA and frame transmission is complete The TxBD fields are detailed in Table 11 35 Offset 2 Data Length Written by the FEC Data length is the number of octets written by the FEC into this BD s data buffer if L 0 the value is equal to R_BUFF_SIZE or the length of the frame including C...

Page 257: ...y valid if L 1 The FEC had to defer while trying to transmit a frame This bit is not set if a collision occurs during transmission 8 HB Heartbeat error Written by the FEC and is valid only if L 1 The collision input was not asserted within the heartbeat window following the completion of transmission Cannot be set unless the HBC bit is set in the X_CNTRL register 7 LC Late collision Written by the...

Page 258: ...scriptors and buffers Separate interrupt vectors for Rx Tx and non time critical interrupts Interrupt priority is set in the interrupt controller The formula for calculating E_MDC clock frequency differs between MCF5272 and MPC860T MCF5272 E_MDC_FREQUENCY system frequency 4 MII_SPEED MPC860T E_MDC_FREQUENCY system frequency 2 MII_SPEED NOTE MCF5272 ethernet controller signal names are generally id...

Page 259: ...s definitions of many of the terms found here NOTE Unless otherwise stated all mention of the USB specification refers to revision 1 1 12 1 Introduction The universal serial bus USB is an industry standard extension to the PC architecture The USB controller on the MCF5272 supports device mode data communication between itself and a USB host device typically a PC One host and up to 127 attached per...

Page 260: ...tomatic processing of USB standard device requests CLEAR_FEATURE GET_CONFIGURATION GET_DESCRIPTOR GET_INTERFACE GET_STATUS SET_ADDRESS SET_CONFIGURATION SET_FEATURE and SET_INTERFACE Supports either internal or external USB transceiver Programmable 512 byte receive and 512 byte transmit FIFO buffers USB device controller with protocol control and administration for up to eight endpoints 16 interfa...

Page 261: ...SB function endpoint but cannot serve as a USB host 12 2 1 USB Module Architecture A block diagram of the USB module is shown in Figure 12 2 The module is partitioned into five functional blocks These blocks are USB internal transceiver clock generator USB control logic USB request processor and endpoint controllers Figure 12 2 USB Module Block Diagram Clock Generator USB Request Processor 512 Byt...

Page 262: ...sumption USB_VDD may be left unconnected if either of the following is true The USB module is not used An external transceiver is used 12 2 1 2 Clock Generator The USB module requires two clock inputs the system clock and a 48 MHz data clock The data clock source is selectable between the USB_ExtCLK pin or the system clock The clock generator automatically uses the external clock as the data clock...

Page 263: ... endpoints A total of 1024 bytes of dual port RAM are available for transmit and receive FIFO buffers This RAM is partitioned to provide 512 bytes for each direction The user is responsible for configuring the FIFO for each endpoint This configuration is flexible within the following constraints FIFO size must be an integral power of 2 FIFO size must be at least twice the maximum packet size FIFO ...

Page 264: ...vided get_status Returns the current status of the specified device endpoint or interface No user notification is provided no user action required set_address Loads the specified address into USBFAR The control logic begins responding to the new address once the status stage of the request completes successfully No user notification is provided unless debug mode is enabled set_configuration Reads ...

Page 265: ...1018 USB Device Request Data1 Register DRR1 0x101C USB Device Request Data2 Register DRR2 0x1020 Reserved USB Specification Number Register SPECR 0x1024 Reserved USB Endpoint 0 Status Register EP0SR 0x1028 USB Endpoint 0 IN Config Register IEP0CFG 0x102C USB Endpoint 0 OUT Config Register OEP0CFG 0x1030 USB Endpoint 1 Configuration Register EP1CFG 0x1034 USB Endpoint 2 Configuration Register EP2CF...

Page 266: ...gister EP4IMR 0x10A0 Reserved USB Endpoint 5 Interrupt Mask Register EP5IMR 0x10A4 Reserved USB Endpoint 6 Interrupt Mask Register EP6IMR 0x10A8 Reserved USB Endpoint 7 Interrupt Mask Register EP7IMR 0x10AC USB Endpoint 0 Data Register EP0DR 0x10B0 USB Endpoint 1 Data Register EP1DR 0x10B4 USB Endpoint 2 Data Register EP2DR 0x10B8 USB Endpoint 3 Data Register EP3DR 0x10BC USB Endpoint 4 Data Regis...

Page 267: ...umber is issued by the USB host To avoid a false match during intermediate states of a byte write operation to the FNMR Figure 12 4 byte accesses to this register are not supported and cause an access error Figure 12 4 USB Frame Number Match Register FNMR Table 12 4 describes FNMR fields 15 11 10 0 Field FRM Reset 0000_0000_0000_0000 R W Read Addr MBAR 0x1002 Table 12 3 FNR Field Descriptions Bits...

Page 268: ... real time frame monitor register 12 3 2 4 USB Real Time Frame Monitor Match Register RFMMR To avoid intermediate false values in the real time frame monitor match register Figure 12 6 byte accesses are not supported and cause an access error Table 12 4 FNMR Field Descriptions Bits Name Description 15 11 Reserved should be cleared 10 0 FRM_MAT Frame number match value Contains the USB frame number...

Page 269: ...ettings Register ASR Defines which of several possible interfaces is currently active 15 14 13 0 Field RTFM_MAT Reset 0000_0000_0000_0001 R W R W Addr MBAR 0x100E Table 12 6 RFMMR Field Descriptions BIts Name Description 15 14 Reserved should be cleared 13 0 RTFM_MAT Real time frame monitor match Contains the real time frame monitor match value When the RFMR value equals the value in the register ...

Page 270: ...ields in DRR1 and DRR2 are defined in Chapter 9 of the USB Specification See top of page p 12 1 Figure 12 9 USB Device Request Data 1 Register DRR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field IF15_AS IF14_AS IF13_AS IF12_AS IF11_AS IF10_AS IF9_AS IF8_AS Reset 0000_0000_0000_0000 R W Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field IF7_AS IF6_AS IF5_AS IF4_AS IF3_AS IF2_AS IF1_AS IF0_AS R...

Page 271: ...er Only written via the standard SET_CONFIGURATION request by the host 31 16 Field wLength Reset 0000_0000_0000_0000 R W Read 15 0 Field wIndex Reset 0000_0000_0000_0000 R W Read Addr MBAR 0x101C 15 4 3 0 Field SPEC MRN Reset 0001_0001_0000_0001 R W Read Addr MBAR 0x1022 Figure 12 11 USB Specification Number Register SPECR Table 12 9 SPECR Field Descriptions Bits Name Descriptions 15 4 SPEC USB sp...

Page 272: ... EPISR0 DEV_CFG is set 11 WAKE_ST Remote wakeup status Indicates whether the USB module has been enabled to generate remote wakeup resume signaling 1 Enabled The USB host has issued the SET_FEATURE request with the Remote wakeup feature selector set 0 Disabled The USB host has issued the CLEAR_FEATURE request with the remote wakeup feature selector set or has not set this feature since a USB or sy...

Page 273: ..._0000_0000 R W R W Addr MBAR 0x1028 Figure 12 13 USB Endpoint 0 IN Configuration Register IEP0CFG Table 12 11 IEP0CFG Field Descriptions Bits Name Descriptions 31 22 MAX_PACKET Maximum packet size Must be written with the maximum packet size defined in the device descriptor for endpoint 0 or the endpoint descriptors for other endpoints 21 Reserved should be cleared 20 11 FIFO_SIZE Size of the FIFO...

Page 274: ... control register provides both module level and endpoint 0 specific control bits 0 9 functions 31 22 21 20 16 Field MAX_PACKET FIFO_SIZE Reset 0000_0000_0000_0000 R W R W 15 11 10 9 0 Field FIFO_SIZE FIFO_ADDR Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x102C Figure 12 14 USB Endpoint 0 OUT Configuration Register 31 22 21 20 16 Field MAX_PACKET FIFO_SIZE Reset 0000_0000_0000_0000 R W R W 15 10 9...

Page 275: ...dress 0 Normal operation 1 Enable debug mode functions 17 WOR_LVL Wake on ring level select Selects the active level of INT1 for the wake on ring function 0 Wake on ring function is invoked when INT1 pin is 0 1 Wake on ring function is invoked when INT1 pin is 1 16 WOR_EN Wake on ring enable Generates a RESUME when the active level is detected on INT1 pin 0 Wake on ring function disabled 1 Wake on...

Page 276: ...e registers are initialized and the descriptors are copied into the configuration RAM 0 Disable USB module 1 Enable USB module 10 CFG_RAM_VAL Enable USB configuration RAM Notifies the USB module that the user has loaded the configuration RAM Must be set in order for the USB module to process the USB standard device requests that access the configuration RAM These requests are GET_DESCRIPTOR SET_CO...

Page 277: ...the selected level 00 FIFO 25 Empty 01 FIFO 50 Empty 10 FIFO 75 Empty 11 FIFO 100 Empty 1 IN_DONE This bit controls the USB s response to IN tokens from the host This bit is set at Reset and must be cleared by software when the last byte of a transfer has been written to the IN FIFO This bit is then subsequently set by the USB core when an end of transfer EOT event occurs indicating that the trans...

Page 278: ...es a CRC error on the next non zero length data packet transmitted The CRC_ERR bit must be set again in order to generate another CRC error This bit is only valid for IN endpoints This command bit is write only and always returns 0 when read 0 Default Value 1 CRC error generation if DEBUG 1 6 ISO_MODE Isochronous transfer mode This bit must be set when the endpoint is configured for isochronous mo...

Page 279: ... endpoint configuration b A zero length IN packet is transmitted This occurs when the previously transmitted IN packet was full and no more data remains in the IN FIFO Hence a single zero length packet must be sent to indicate EOT 0 CPU has completed writing to the IN FIFO and transfer is in progress The USB module sends all the data in the FIFO or a zero length packet when the FIFO is empty 1 Tra...

Page 280: ... 18 USB Endpoint 0 Interrupt Mask EP0IMR and General Endpoint 0 Interrupt Registers EP0ISR Table 12 14 EP0IMR and EP0ISR Field Descriptions Bits Name Description 31 17 Reserved should be cleared 16 DEV_CFG Device configuration change interrupt Set when a device configuration change has been received The USB standard device requests SET_CONFIGURATION and SET_INTERFACE generate a DEV_CFG interrupt A...

Page 281: ...pt pending 1 USB resume signal detected 9 SUSPEND Suspend Set when the USB module detects a suspend state on the USB data lines The USB suspends when the bus is idle for at least 3 ms 0 No interrupt pending 1 USB suspend state detected 8 RESET USB Reset Set when the USB module detects a USB reset A USB reset is caused by a single ended zero SE0 greater than 2 5 µs A USB reset has no effect on the ...

Page 282: ...No interrupt pending 1 IN packet sent successfully 2 UNHALT Unhalt This bit is set when the endpoint 0 HALT_ST bit is cleared by a SETUP packet or USB reset 0 No interrupt pending 1 Endpoint halt cleared 1 HALT Halt This bit is set when the endpoint 0 HALT_ST bit is set due to a STALL response to the host 0 No interrupt pending 1 Endpoint halted 0 IN_LVL IN FIFO threshold level This bit indicates ...

Page 283: ...4 EOT End of transfer interrupt Set when the end of a transfer has been reached An EOT interrupt is generated when a packet with a size less than the maximum packet size or the first zero length packet following maximum size packets is sent or received For OUT endpoints the EPDPn must be read before clearing this interrupt in order to determine the number of bytes of remaining data in the FIFO for...

Page 284: ...hould be cleared 4 0 Interrupt mask These bits are set when the user wants to activate the interrupt source for the specific bit Refer to Table 12 15 for a description of each interrupt source 1 Interrupt Enabled 0 Interrupt Disabled 31 16 Field DATA Reset 0000_0000_0000_0000 R W R W 15 0 Field DATA Reset 0000_0000_0000_0000 R W R W Addr MBAR 0x10AC 0x10B0 0x10B4 0x10B8 0x10BC 0x10C0 0x10C4 0x10C8...

Page 285: ...d in Chapter 9 of the USB specification and any relevant class specification NOTE The USB descriptors use little endian format for word and longword fields The MCF5272 uses big endian format for 15 9 8 0 Field DATA_PRES Reset 0000_0000_0000_0000 R W Read Addr MBAR 0x10CE 0x10D2 0x10D6 0x10DA 0x10DE 0x10E2 0x10E6 0x10EA Table 12 18 EPnDPR Field Descriptions Bits Name Description 15 9 Reserved shoul...

Page 286: ...the same time Only one setting for a particular interface is effective at any time 12 3 3 2 USB Device Configuration Example The example descriptor structure in Figure 12 23 shows a device with three different configurations Refer to Chapter 9 of the USB Specification for information on the contents of each descriptor Figure 12 23 Example USB Configuration Descriptor Structure This example is desc...

Page 287: ... the time between accesses and whether the previous FIFO access was for the same endpoint After a longword access to an endpoint s FIFO the next longword in the FIFO is cached for a quicker access time on the next longword read This mechanism is reset every time another endpoint is accessed Table 12 19 shows the access times for the FIFOs 12 3 4 3 Configuration RAM The configuration RAM is longwor...

Page 288: ...n and Interface Changes Although the USB module handles the SET_CONFIGURATION and SET_INTERFACE requests the user is still required to perform some initialization when the configuration or alternate settings change A configuration or alternate setting change is signaled by the DEV_CFG interrupt The following steps are required to service the DEV_CFG interrupt 1 Read EPSR0 and ASR to determine the ...

Page 289: ...uration with a variety of endpoint types and packet sizes is shown in Table 12 20 12 4 4 Data Flow The handling of the data flow to and from each endpoint can be divided between isochronous and non isochronous endpoints Isochronous endpoints are designed to transfer streaming data which is continuous and real time in creation delivery and consumption The timely delivery of isochronous data is ensu...

Page 290: ...hat can be written to the FIFO Normally only one packet should be written unless the software does not service the EOP immediately 5 Write data to the FIFO to fill it or until all of the data for the transfer has been written 6 Repeat steps 5 7 until all of the data for the transfer has been written to the FIFO 7 Clear EPnCTL IN_DONE 8 Wait for the EOT interrupt or poll the EOT bit The user can no...

Page 291: ...ochronous endpoints as isochronous endpoints do not have any error detection or flow control mechanisms If the packet size is larger than the FIFO size using interrupts is required 12 4 4 2 1 IN Endpoints The user should write one packet of data to the IN FIFO per frame If an ASOF interrupt occurs the user may wish to discard the data for the frame The following example demonstrates how to handle ...

Page 292: ...sly if an error was encountered while processing the request 12 4 6 REMOTE WAKEUP and RESUME Operation The MCF5272 supports USB RESUME initiated from three different sources Two of the sources are for remote wakeup capability The three different resume mechanisms are listed below The user sets EP0CTL RESUME The USB module responds to this only if the USB is in the suspended state and EP0SR WAKE_ST...

Page 293: ...an error processing a request A halted endpoint can be cleared in several different ways CLEAR_FEATURE request with the endpoint halt feature selector set A USB reset signal A SET_CONFIGURATION or SET_INTERFACE request On control endpoints a SETUP token for the next request 12 5 Line Interface The recommended line interface is shown in Figure 12 24 The transistor used to control the 1 5 kΩ pull up...

Page 294: ... radio frequency radiated noise Bypass capacitors should be connected between the Vdd and GND pairs with minimal trace length These capacitors help supply the instantaneous currents of the digital circuitry in addition to decoupling the noise that may be generated by other sections of the device or other circuitry on the power supply Use short wide low inductance traces to connect all of the GND p...

Page 295: ...general circuit interface GCI or interchip digital link IDL physical layer protocols This module is primarily intended to facilitate designs that include ISDN integrated services digital network interfaces The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN transceivers codecs and other peripherals There are three sets of pins for these interfaces Port 0 h...

Page 296: ...ck DCL These pins are unidirectional inputs Din0 and Dout0 are dedicated pins for port 0 Port 1 Connects through pin set 1 Operates as a master or slave port In slave mode an external device must source FSC FSR and DCL In master mode DCL1 and FSC1 FSR1 are outputs These signals are in turn derived from the DCL0 and FSC FSR from port 0 For port 1 to function in master mode port 0 must be enabled wi...

Page 297: ...slave mode or GDCL when port 1 is in master mode A delayed frame sync DFSC3 is derived from FSC1 and is fed to the port 3 IDL GCI block Programming the port 3 sync delay register P3SDR allows it to be synchronized with an offset frame sync offset with respect to the port 1 GCI IDL block Port 3 can also have dedicated data in and data out pins DIN3 and DOUT3 of pin set 3 see Section 13 5 7 Port Con...

Page 298: ...ps D channel Frames of B1 and B2 channels are packed together to form longwords 32 bits Frames of D channels are packed together to form bytes For channels B and D this requires CPU service at a 2 KHz rate because it requires four frames to fill the 32 bit B channel register and the 8 bit D channel register D Channel B1 Shift Register B2 Shift Register D Shift Register DIN DCL B2 Channel B1 Channe...

Page 299: ... registers and shadow registers are initialized to all ones Figure 13 3 GCI IDL B Channel Receive Data Register Demultiplexing 13 2 2 GCI IDL B and D Channel Transmit Data Registers Figure 13 4 GCI IDL Transmit Data Flow The maximum transmission rate for each GCI IDL port is 144 Kbps the sum of two 64 Kbps B channels and one 16 Kbps D channel Frames of B1 B2 and D channels are packed together in a...

Page 300: ...ting bits from the lsb The look up table in the software HDLC on this device transmits the lsb first 13 2 3 1 B Channel Unencoded Data Because unencoded voice data appears on the physical interface most significant bit msb first the msb is left aligned in the transmit and receive shift register that is the first bit of B channel received data is aligned in the msb position as shown in Figure 13 6 ...

Page 301: ...n the lsb position through to the last received bit of a byte that is aligned in the msb position The ordering of the bytes over four frames within the longword register is as for unencoded data that is the first frame is aligned in the MSB through to the fourth frame which is aligned in the LSB position See Figure 13 6 13 2 3 3 D Channel HDLC Encoded Data When the incoming D channels contain HDLC...

Page 302: ... encoded B channel data it is assumed unencoded D channel information is presented on the physical line msb first The msb is left aligned in the transmit and receive shift register that is the first bit received is aligned in the msb position through to the last received bit of a byte that is aligned in the lsb position A D channel byte is formed by concatenating two D bits from each frame over fo...

Page 303: ...n GCI mode the PLIC ports do not support any other form of D channel contention such as the indirect mode found on the Motorola MC145574 In GCI mode the DGRANT pin function found in IDL mode is disabled and the pin can be defined for other functions Please note that the D channel periodic interrupts in both the receive and transmit direction are not disabled even though the shift register is disab...

Page 304: ...by sending data to the transmitter and checking data assembled by the receiver In this manner correct channel operations can be assured Also both transmitter and CPU to receiver communications continue normally in this mode While in this mode the receive Din pin is ignored the transmit Dout is held marking and the receiver is clocked by the transmitter clock 13 2 4 3 Remote Loopback Mode The chann...

Page 305: ...e 13 10 that due to the double buffering through the PLIC shadow register frame n is written to the PLIC transmit register during the interrupt service routine of the previous frame frame n 1 Similarly on the receive side frame n is read from the PLIC receive register during the interrupt service routine of the following frame frame n 2 Figure 13 10 shows that the minimum delay through the PLIC wh...

Page 306: ...rrupt Control There are a number of control mechanisms for the periodic and aperiodic interrupts on the PLIC Clearing the ON OFF bit in the port configuration register Section 13 5 7 Port Configuration Registers P0CR P3CR turns the port off and masks all periodic and aperiodic interrupts for the affected port Clearing the enable bits ENB1 or ENB2 in the port configuration register masks the period...

Page 307: ...z and the synthesized frame sync Gen_FSC must be set A Gen_FSC of 8 KHz is assumed This division ratio is selected by means of FDIV 2 0 Finally the clock generation block should be taken out of bypass by setting PCSR NBP The above settings can be made by a single write of the 16 bit value 0x802B to PCSR The following restrictions should be observed when using the clock generator module The smalles...

Page 308: ...ugh programmable delays 2 and 3 referenced to DFSC1 Note well the following Port 0 Port 1 Port 2 Port 3 Prog Delay 0 Prog Delay 1 Prog Delay 2 DCL1 FSC1 Prog Delay 3 DFSC2 DCL1 DCL1 DFSC2 DFSC3 DCL1 GDCL1_OUT FSC1 FSR1 DFSC1 P1CR M S DCL0 URT1_CLK PA8 FSC0 FSR0 GCI IDL GCI IDL GCI IDL GCI IDL DCL0 DFSC0 SFSC Gen FSC0 FSC1 P1CR SFSM P0CR M2 M0 2 KHz to CPU DFSC1 DFSC0 Pin Mux 0 Pin Mux 1 P0SDR 15 0...

Page 309: ... D Data Receive P3DRR 0x0328 Port0 B1 Data Transmit P0B1TR 0x032C Port1 B1 Data Transmit P1B1TR 0x0330 Port2 B1 Data Transmit P2B1TR 0x0334 Port3 B1 Data Transmit P3B1TR 0x0338 Port0 B2 Data Transmit P0B2TR 0x033C Port1 B2 Data Transmit P1B2TR 0x0340 Port2 B2 Data Transmit P2B2TR 0x0344 Port3 B2 Data Transmit P3B2TR 0x0348 Port0 D Data Transmit P0DTR Port1 D Data Transmit P1DTR Port2 D Data Transm...

Page 310: ...to MBAR 0x30C for P3B1RR See Section 13 2 3 GCI IDL B and D Channel Bit Alignment for the frame and bit alignment within the 32 bit word 0x036C Port2 GCI monitor Tx P2GMT Port3 GCI monitor Tx P3GMT 0x0370 Reserved GCI monitor Tx status PGMTS GCI monitor Tx abort PGMTA Reserved 0x0374 Port0 GCI C I Rx P0GCIR Port1 GCI C I Rx P1GCIR Port2 GCI C I Rx P2GCIR Port3 GCI C I Rx P3GCIR 0x0378 Port0 GCI C ...

Page 311: ...ve data registers 13 5 3 D Data Receive Registers P3DRR P0DRR All bits in these registers are read only and are set on hardware or software reset The PLRD registers contain the last four frames of D channel receive data packed from the least significant bit lsb to the most significant bit msb for each of the four physical 31 24 23 16 Field Frame 0 Frame 1 Reset 1111_1111 1111_1111 R W Read Only 15...

Page 312: ...r port 0 P1B1TR is B1 transmit for port 1 and so on The data are packed from LSB to MSB These registers are aligned on long word boundaries from MBAR 0x328 for P0B1TR to MBAR 0x334 for P3B1TR See Section 13 2 3 GCI IDL B and D Channel Bit Alignment for the frame and bit alignment within the 32 bit word 31 24 23 16 Field P0DRR P1DRR Reset 1111_1111 1111_1111 R W Read Only 15 8 7 0 Field P2DRR P3DRR...

Page 313: ...ters P3DTR P0DTR All bits in these registers are read write and are set on hardware or software reset The PLTD registers contain four frames of D channel transmit data packed from lsb to msb for each of the four physical ports on the MCF5272 P0DTR is the D channel byte for port 0 P1DTR the D channel for port 1 and so on The four byte addressable 8 bit registers P3DTR P0DTR are packed to form one 3...

Page 314: ...FF DMX SHB2 SHB1 ENB2 ENB1 Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x350 P0CR 0x35 P1CR 0x352 P2CR 0x356 P3CR Figure 13 19 Port Configuration Registers P0CR P3CR Table 13 2 P0CR P3CR Field Descriptions Bits Name Description 15 ON OFF 0 Port is off and in a steady state condition In this state the B and D channels on the transmit side are high impedance when in GCI IDL The receive regist...

Page 315: ...nsibility of the CPU to clear the ACT bit when normal operation on Dout is required This bit is intended to be used to request activation from the upstream DCL FSC driver Periodic interrupts commence as soon as the upstream device generates DCL provided the appropriate interrupts such as IE B1RIE and so on are enabled for the port 7 DMX Data multiplex 0 port 3 Dout and Din are multiplexed onto Dou...

Page 316: ...r software reset The PLICR registers contain interrupt configuration bits for each of the four ports on the MCF5272 7 6 5 4 3 2 1 0 Field LM3 LM2 LM1 LM0 Reset 0000_0000 R W Read Write Addr MBAR 0x38F Figure 13 20 Loopback Control Register PLCR Table 13 3 PLCR Field Description Bits Name Description 7 6 LM3 Loopback mode control port 3 00 Normal 01 Auto echo 10 Local Loopback 11 Remote Loopback 5 ...

Page 317: ...it 0 Interrupt masked 1 Interrupt enabled 7 6 Reserved should be cleared 5 DTIE D transmit interrupt enable 0 Interrupt masked 1 Interrupt enabled Interrupt occurs when the corresponding PLPSR DTDE or PLPSR DTUE is set 4 B2TIE B2 transmit interrupt enable 0 Interrupt masked 1 Interrupt enabled Interrupt occurs when the corresponding PLPSR B2TDE or PLPSR B2TUE is set 3 B1TIE B1 transmit interrupt e...

Page 318: ... the data in the PLTB1 transmit data register for the respective port was transferred to the transmit shadow register which was already empty indicated by B1TDE B1TUE is automatically cleared when the PLPSR register has been read by the CPU 8 DROE D Channel data receive overrun error This bit is set when the data in the D receive shadow register for the respective port has been transferred to the ...

Page 319: ...s that the B2 receive data register for the respective port is full B2RDF is cleared when the CPU reads the receive data register PLRB2 0 B1RDF B1 receive data full This bit indicates that the B1 receive data register for the respective port is full B1RDF is cleared when the CPU reads the receive data register PLRB1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field GCR 3 GCT 3 GMR 3 GMT 3 GCR 2 GCT 2 GM...

Page 320: ... 8 4 0 GMTn GCI monitor transmitted When set this bit indicates that the monitor channel transmit register is empty An interrupt is queued when this bit is set if the GMT interrupt enable bit has been set in the corresponding PLICR register The GMT bit and associated interrupt are automatically cleared when the PGMTS register has been read by the CPU 15 11 10 9 8 7 0 Field EOM AB MC M Reset 0000_0...

Page 321: ...0000_0000 R W Read Write Addr MBAR 0x368 P0GMT 0x36A P1GMT 0x36C P2GMT 0x36E P3GMT Figure 13 25 GCI Monitor Channel Transmit Registers P0GMT P3GMT Table 13 8 P0GMT P3GMT Field Descriptions Bits Name Description 15 10 Reserved should be cleared 9 L Last 0 Default reset value 1 Set by the CPU Indicates to the monitor channel controller to transmit the end of message signal on the E bit Both PnGMT L ...

Page 322: ...6 5 4 3 0 Field AR3 AR2 AR1 AR0 Reset 0000_0000 R W Read Write Addr MBAR 0x372 Figure 13 26 GCI Monitor Channel Transmit Abort Register PGMTA Table 13 9 PGMTA Field Descriptions Bits Name Description 7 AR3 Abort request port 3 0 Default reset value 1 Set by the CPU this bit causes the monitor channel controller to transmit the end of message signal on the E bit Automatically cleared by the monitor...

Page 323: ...t 2 See ACK3 5 ACK1 Acknowledge port 1 See ACK3 4 ACK0 Acknowledge port 0 See ACK3 3 AB3 Abort port 3 0 Default reset value 1 Indicates to the CPU that the GCI controller has aborted the current message This bit is automatically cleared by the CPU reading the register When the GCI controller sets this bit it also clears the AR bit in the PGMTA register the ACK bit in the GMTS register and the L an...

Page 324: ...available for processing It is automatically cleared by a CPU read The clearing of this bit by reading this register also clears the aperiodic GCR interrupt 27 24 19 16 11 8 3 0 C3 C0 C I bits These four bits are received on the GCI or SCIT channel 0 When a change in the C I data value is received in two successive frames it is interpreted as being valid and is passed on to the CPU via this regist...

Page 325: ...T0 0x379 PLGCT1 0x37A PLGCT2 0x37B PLGCT3 Figure 13 29 GCI C I Channel Transmit Registers P0GCIT P3GCIT Table 13 12 P0GCIT P3GCIT Field Descriptions Bits Name Description 31 29 23 21 15 13 7 5 Reserved should be cleared 28 20 12 4 R Ready This bit is set by the CPU to indicate to the C I channel controller that data is ready for transmission The transition of this bit from a 0 to a 1 starts the C ...

Page 326: ... ACK bit is automatically cleared by the CPU when the PGCITSR register has been read 2 ACK2 Acknowledge port 2 See ACK3 1 ACK1 Acknowledge port 1 See ACK3 0 ACK0 Acknowledge port 0 See ACK3 7 6 5 4 3 2 1 0 Field DG1 DG0 DC3 DC2 DC1 DC0 Reset 0000_0000 R W Read Only Addr MBAR 0x383 Figure 13 31 D Channel Status Register PDCSR Table 13 14 PDCSR Field Descriptions Bits Name Description 7 6 Reserved s...

Page 327: ...leared 11 9 SHDD D channel shift direction 0 D channel data is msb first The first bit received is assumed to be the most significant bit and is loaded into the msb position of the D channel receive register for the respective port SHDD 1 configures the shift direction for ports 1 2 and 3 SHDD 0 configures the shift direction for port 0 1 D channel data is lsb first for the D channel The first bit...

Page 328: ...bits in this register are read write and are cleared on hardware or software reset PCSR controls the PLIC clock generation block Please refer to Section 13 3 PLIC Timing Generator for certain restrictions on the use of the clock generation block 15 14 13 10 9 0 Field FSW1 FSW0 SD Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x394 P0SDR 0x396 P1SDR 0x398 P2SDR 0x39A P3SDR Figure 13 33 Sync De...

Page 329: ...ld Descriptions Bits Name Description 15 NBP Non bypass mode select for the clock generation module 0 The clock generation module is bypassed Gen_FSC and GDCL are connected to FSC0 and DCL0 1 Selects non bypassed mode Gen_FSC and GDCL are synthesized from the incoming FSC0 or DCL0 14 8 Reserved should be cleared 7 6 CKI Clock select Input Selects the source clock for the clock generation block 00 ...

Page 330: ... PLCRn G S If port 1 is used program whether the 2 KHz frame interrupt is to be derived from port 0 or port 1 PLCRn FSM If port 1 is used program whether it receives as inputs DCL and FSC or whether it drives these signals as outputs If the port is in GCI mode the PLCRn ACT bit may be set if GCIActivation should be requested If port 3 is used program the PLCRn DMX bit if this port is routed throug...

Page 331: ...d B2 disabled move w d0 P1CR A5 write to P1CR register The above code segment is an example only 13 6 2 2 Interrupt Configuration Example The PLICR registers should be configured according to the specific interrupts periodic and aperiodic required for each port In addition the port interrupt enable PLICRn IE should be set for each active port prior to receiving interrupts Assuming port 1 is config...

Page 332: ...A5 write value to PLICR 13 6 3 Example 1 ISDN SOHO PBX with Ports 0 1 2 and 3 In this example all four ports are used to connect an external transceiver and six CODECs Port 0 and port 1 are programmed in slave mode An external transceiver MC145574 is connected to port 0 Port 1 2 and 3 are used to connect up to six external PCM CODECs GCI only Port 0 only IE enabled Reserved DTIE enabled B2TIE disa...

Page 333: ...e sync with reference to FSC1 Similarly CODECs 5 and 6 are connected to DFSC3 which is the output of programmable delay 3 Programmable delay 3 generates a delayed frame sync also with reference to FSC1 The MC14LC5480 CODECs when in IDL mode may be programmed using the FSR pin to select whether the CODEC Din1 Dout1 FSC1 DCL1 MC145574 MC14LC5480 CODEC 4 CODEC5 Interface 1 DFSC2 DFSC3 CODEC6 Tx DT DT...

Page 334: ...nterface the delayed frame syncs are programmed to synchronize the CODECs on non overlapping time slots CODEC 1 transmits and receives in the B1 time slot CODEC 2 transmits and receives in the B2 time slot which starts 10 DCL cycles later and so on for the other CODECs CODECs 3 and 4 are synchronized to DFSC2 which is generated 20 DCL cycles after FSC1 by loading the programmable delay 2 register ...

Page 335: ...ng the data on the U transceiver s IDL interface CODECs 1 and 2 are connected to delayed frame sync 2 DFSC2 which is the output of programmable delay 2 Programmable delay 2 generates a delayed frame sync with reference to FSC1 Similarly CODECs 3 and 4 are connected to DFSC3 which is the output of programmable delay 3 Programmable delay 3 generates a delayed frame sync also with reference to FSC1 T...

Page 336: ...hannel and the start of the B3 channel For example let us say this is 1 DCL clocks long This defines the programmable delay 1 value to be 20 19 1 or 0x0014 The DFSC3 signal synchronizes CODECs 3 and 4 and the rising edge of this frame sync occurs 20 clocks after DFSC2 therefore 40 DCL clocks after FSC1 This defines the value for programmable delay 3 to be 40 19 1 20 or 0x0028 13 6 5 Example 3 Two ...

Page 337: ...onnected to transceiver two Figure 13 42 shows an example of the IDL bus timing relationship of the S T transceivers when in standard IDL2 8 bit mode with a common frame sync Figure 13 42 Standard IDL2 8 Bit mode MC145574 1 Interface 1 Tx Rx IDL SYNC IDL CLK Din0 Dout0 FSC0 DCL0 Interface 0 DGrant DRequest DGNT0 DREQ0 Din1 Dout1 FSC1 DCL1 DGNT1 DREQ1 Tx Rx IDL SYNC IDL CLK DGrant DRequest MC145574...

Page 338: ...13 44 MCF5272 User s Manual Application Examples ...

Page 339: ...SPI are indirectly accessible using address and data registers Functionality is very similar but not identical to the QSPI portion of the QSM queued serial module implemented in the MC68332 14 2 Features Programmable queue to support up to 16 transfers without user intervention Supports transfer sizes of 8 to 16 bits in 1 bit increments Four peripheral chip select lines for control of up to 15 dev...

Page 340: ...rted simultaneously Although QSPI_CS 0 3 will function as simple chip selects in most applications up to 15 ports can be selected by decoding them with an external 4 to 16 decoder Figure 14 1 QSPI Block Diagram Note that chip selects QSPI_CS 3 1 are multiplexed with other pin functions QSPI_Dout QSPI_CLK and QSPI_CS0 are multiplexed with MCF5272 configuration inputs that only function during syste...

Page 341: ...d sets the completion flag in the QSPI interrupt register QIR SPIF to signal their completion Optionally QIR SPIFE can be enabled to generate an interrupt The QSPI uses four queue pointers The user can access three of them through fields in QSPI wrap register QWR The new queue pointer QWR NEWQP points to the first command in the queue An internal queue pointer points to the command currently being...

Page 342: ...o eight but can be set to any value from 8 to 16 by writing a value into the BITSE field of the command RAM QCR BITSE 14 4 1 QSPI RAM The QSPI contains an 80 byte block of static RAM that can be accessed by both the user and the QSPI This RAM does not appear in the MCF5272 memory map because it can only be accessed by the user indirectly through the QSPI address register QAR and the QSPI data regi...

Page 343: ...on word is used consistently and exclusively to designate a 16 bit data unit The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable length data units To simplify these discussions the functional unit is referred to as a word regardless of length QWR CPTQP shows which queue entries have been executed The user can query this field to dete...

Page 344: ...eue execution proceeds from the address in QWR NEWQP through the address in QWR ENDQP The QSPI executes a queue of commands defined by the control bits in each command RAM entry which sequence the following actions chip select pins are activated data is transmitted from transmit RAM and received into the receive RAM the synchronous transfer clock QSPI_CLK is generated Before any data transfers beg...

Page 345: ...od from the negation of the QSPI_CS signals until the start of the next transfer The delay after transfer can be used to provide a peripheral deselect interval A delay can also be inserted between consecutive transfers to allow serial A D converters to complete conversion There are two transfer delay options the user can choose to delay a standard period after serial transfer is complete or can sp...

Page 346: ...er and transmitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits has been transferred the QSPI stores the working queue pointer value in QWR CPTQP increments the working queue pointer and loads the next data for transfer from the transmit RAM The command pointed to by the incremented working queue pointer is executed next unless...

Page 347: ...ters They are the QSPI mode register QMR QSPI delay register QDLYR QSPI wrap register QWR QSPI interrupt register QIR QSPI address register QAR and the QSPI data register QDR There are a total of 80 bytes of memory used for transmit receive and control data This memory is accessed indirectly using QAR and QDR Registers and RAM are written and read by the CPU 14 5 1 QSPI Mode Register QMR The QMR r...

Page 348: ...for each entry in the queue Value Bits per transfer 0000 16 0001 0111 Reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 9 CPOL Clock polarity Defines the clock polarity of SCK 0 The inactive state value of QSPI_CLK is logic level 0 1 The inactive state value of QSPI_CLK is logic level 1 8 CPHA Clock phase Defines the QSPI_CLK clock phase 0 Data captured on the leading edge of ...

Page 349: ...e command RAM Automatically cleared by the QSPI when a transfer completes The user can also clear this bit to abort transfer unless QIR ABRTL is set The recommended method for aborting transfers is to set QWR HALT 14 8 QCD QSPILCK Delay When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition 7 0 DTL D...

Page 350: ...PI wraps to in wraparound mode 0 Wrap to RAM entry zero 1 Wrap to RAM entry pointed to by QWR NEWQP 12 CSIV QSPI_CS inactive level 0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer that is inactive state is 0 chip selects are active high 1 QSPI chip select outputs return to one when not driven from the value in the current c...

Page 351: ... cleared by writing to the QDLYR QDLYR SPE is only cleared by the QSPI when a transfer completes 11 WCEFE Write collision interrupt enable Interrupt enable for WCEF Setting this bit enables the interrupt and clearing it disables the interrupt 10 ABRTE Abort interrupt enable Interrupt enable for ABRT flag Setting this bit enables the interrupt and clearing it disables the interrupt 9 Reserved shoul...

Page 352: ...isters QCR0 QCR15 The command RAM is accessed using the upper byte of QDR The QSPI cannot modify information in command RAM There are 16 bytes in the command RAM Each byte is divided into two fields The chip select field enables external peripherals for transfer The command field provides transfer operations NOTE The command RAM is accessed only using the most significant byte of QDR and indirect ...

Page 353: ...Figure 14 10 Command RAM Registers QCR0 QCR15 Table 14 7 gives QCR field descriptions Table 14 7 QCR0 QCR15 Field Descriptions Bits Name Description 15 CONT Continuous 0 Chip selects return to inactive level defined by QWR CSIV when transfer is complete 1 Chip selects remain asserted after transfer is complete 14 BITSE Bits per transfer enable 0 Eight bits 1 Number of bits set in QMR BITS 13 DT De...

Page 354: ... low in this example 7 Write QAR with 0x0000 to select the first transmit RAM entry 8 Write QDR with sixteen 12 bit words of data 9 Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15 10 Set QDLYR SPE to enable the transfers 11 Wait until the transfers are complete QIR SPIF is set when the transfers are complete 12 Write QAR with 0x0010 to select the first receive R...

Page 355: ...consists of a timer mode register TMRn a timer capture register TCRn a 16 bit timer counter TCNn a timer reference register TRRn and a timer event register TERn The TMRs contain the prescaler value programmed by the user The four timer units have the following features Maximum period of 4 seconds at 66 MHz 15 nS resolution at 66 MHz Programmable sources for the clock input including external clock...

Page 356: ...ding timer mode register TMR0 TMR3 The prescaler is programmed to divide the clock input by values from 1 to 256 The output of the prescaler is used as an input to the 16 bit counter Data 16 Timer Clock Generator Divider Timer Mode Register TMR0 Prescaler Mode Bits Timer Counter TCN0 15 0 Timer Reference Register TRR0 15 0 Capture Register TCR0 15 0 15 0 Capture Detection System Clock or System Cl...

Page 357: ...MR OM This signal can be an active low pulse or a toggle of the current output under program control The TCRs are used to latch counter values when the corresponding input capture edge detector detects a defined transition of TIN0 TIN1 URT0_RxD or URT1_RxD The type of transition triggering the capture is selected by the capture edge bits TMR CE A capture or reference event sets the TER bit and gen...

Page 358: ...7 2 Port Control Registers 4 ORI Output reference interrupt enable 0 Disable interrupt for reference reached does not affect interrupt on capture function 1 Enable interrupt upon reaching the reference value If ORI is 1 when the TER REF is set an immediate interrupt occurs 3 FRR Free run restart 0 Free run Timer count continues to increment after the reference value is reached 1 Restart Timer coun...

Page 359: ...t regardless of the corresponding interrupt enable bits ORI and CE in the TMRn Writing a 1 to a bit clears it writing 0 has no effect Both bits must be cleared before the timer can negate the request to the interrupt controller Both bits may be cleared simultaneously Table 15 2 describes TERn fields 15 0 Field CAP 16 bit capture counter value Reset 0000_0000_0000_0000 R W Read Only Addr MBAR 0x200...

Page 360: ...TRR value 1 The counter reached the TRR value TMR ORI is used to enable the interrupt request caused by this event Write a 1 to this bit to clear the event condition 0 CAP Capture event 0 The counter value has not been latched into the TCR 1 The counter value is latched in the TCR TMR CE is used to enable capture and the interrupt request caused by this event Write a 1 to this bit to clear the eve...

Page 361: ...ull duplex asynchronous synchronous receiver and transmitter deriving an operating frequency from CLKIN or an external clock of the correct frequency URT_CLK The transmitter converts parallel data from the CPU to a serial bit stream inserting appropriate start stop and parity bits It outputs the resulting stream on the channel transmitter serial data output TxD See Section 16 5 2 1 Transmitting Th...

Page 362: ...ho local loop back or remote loop back mode Automatic wake up mode for multidrop applications Eight maskable interrupt conditions Parity framing and overrun error detection False start bit detection Line break detection and generation Detection of breaks originating in the middle of a character Start end break interrupt status Autobaud capability The MCF5272 UART modules are identical to those on ...

Page 363: ...6 15 8 7 0 UART0 UART1 0x100 0x140 UART mode registers1 UMR1n p 16 5 UMR2n p 16 6 0x104 0x144 Read UART status registers USRn p 16 7 Write UART clock select register1 UCSRn p 16 8 0x108 0x148 Read Do not access 2 Write UART command registers UCRn p 16 9 0x10C 0x14C UART Read UART receiver buffers URBn p 16 11 UART Write UART transmitter buffers UTBn p 16 11 0x110 0x150 Read UART input port change ...

Page 364: ...port registers UIPn p 16 18 Write Do not access 2 0x138 0x178 Read Do not access 2 Write UART output port bit set command registers UOP1n3 p 16 18 0x13C 0x17C Read Do not access 2 Write UART output port bit reset command registers UOP0n3 p 16 18 1 UMR1n UMR2n and UCSRn should be changed only after the receiver transmitter is issued a software reset command That is if channel operation is not disab...

Page 365: ...on RTS 1 When a valid start bit is received RTS is negated if the UART s FIFO is full RTS is reasserted when the FIFO has an empty position available If RTS is controlled by the fill level of the receiver FIFO via UACRn RTSL this bit should be cleared 6 RxIRQ FFULL Receiver interrupt select 0 RxRDY is the source that generates IRQ 1 FFULL is the source that generates IRQ If more detail on the stat...

Page 366: ...s transmitted PM 11 PM Parity Mode Parity Type PT 0 Parity Type PT 1 00 With parity Even parity Odd parity 01 Force parity Low parity High parity 10 No parity n a 11 Multidrop mode Data character Address character 1 0 B C Bits per character Select the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits 7 6 5...

Page 367: ...les clear to send operation The transmitter checks the state of CTS each time it is ready to send a character If CTS is asserted the character is sent if it is negated the channel TxD remains in the high state and transmission is delayed until CTS is asserted Changes in CTS as a character is being sent do not affect its transmission 3 0 SB Stop bit length control Selects the length of the stop bit...

Page 368: ...eived A D bit 4 OE Overrun error Indicates whether an overrun occurs 0 No overrun occurred 1 One or more characters in the received data stream have been lost OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position When this occurs the character in the receiver shift register and its break detect framing er...

Page 369: ...r Operating Modes show how these commands are used 7 4 3 0 Field RCS TCS Reset 0000_0000 R W Write only Address MBAR 0x104 UCSR0 0x144 UCSR1 Figure 16 5 UART Clock Select Registers UCSRn Table 16 5 UCSRn Field Descriptions Bits Name Description 7 4 RCS Receiver clock select Selects the clock source for the receiver channel 1101 Prescaled CLKIN 1110 URT_CLK divided by 16 1111 URT_CLK 3 0 TCS Transm...

Page 370: ...RB FE PE OE Also used in block mode to clear all error bits after a data block is received 101 RESET BREAK CHANGE INTERRUPT Clears the delta break bit UISRn DB 110 START BREAK Forces TxD low If the transmitter is empty the break may be delayed up to one bit time If the transmitter is active the break starts when character transmission completes The break is delayed until any character in the trans...

Page 371: ... have no effect when the channel s TxRDY 0 and when the transmitter is disabled Figure 16 8 shows UTBn TB contains the character in the transmitter buffer 1 0 RC This field selects a single command 00 NO ACTION TAKEN Causes the receiver to stay in its current mode If the receiver is enabled it remains enabled if disabled it remains disabled 01 RECEIVER ENABLE If the UART module is not in multidrop...

Page 372: ...MBAR 0x110 UIPCR0 0x150 UIPCR1 Figure 16 9 UART Input Port Change Registers UIPCRn Table 16 7 UIPCRn Field Descriptions Bits Name Description 7 5 Reserved should be cleared 4 COS Change of state high to low or low to high transition 0 No change of state since the CPU last read UIPCRn Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 µs occurred on the CTS input UACRn can be pro...

Page 373: ...red 2 1 RTSL RTS level Determines when RTS is negated by the receiver relative to the fullness of the receiver FIFO Note that RTS must first be manually asserted by a write to UOP0n 00 FIFO level control disabled 01 Receiver FIFO 25 full 10 Receiver FIFO 50 full 11 Receiver FIFO 75 full Receiver overrun can be prevented by using the RTS output to control the CTS input of the transmitting device At...

Page 374: ... is cleared by reading UTBn 0 FIFO status indication is disabled or the transmitter status has not changed 1 The transmitter status has changed as programmed in UTFn TXS 3 RxFTO Receiver FIFO timeout 0 No receiver FIFO timeout This bit is cleared by reading all remaining data in the receiver FIFO by receiving another character into the FIFO or if the receiver is disabled The count to timeout is re...

Page 375: ...tomatically loaded into UDUn and UDLn 16 3 13 UART Transmitter FIFO Registers UTFn The UTFn registers contain control and status bits for the transmitter FIFO Note that some bits are read only 7 0 Field Divider LSB Reset 0000_0000 R W Write only Address MBAR 0x11C UDL0 0x15C UDL1 Figure 16 13 UART Divider Lower Registers UDLn 7 0 Field Autobaud MSB Reset 0000_0000 R W Read only Address MBAR 0x120 ...

Page 376: ...t transmitter FIFO status indication in UISRn 01 Transmitter FIFO 25 empty 10 Transmitter FIFO 50 empty 11 Transmitter FIFO 75 empty When read these bits indicate the emptiness level of the FIFO 00 Transmitter FIFO 25 empty 01 Transmitter FIFO 25 empty 10 Transmitter FIFO 50 empty 11 Transmitter FIFO 75 empty 5 FULL Transmitter FIFO full 0 Transmitter FIFO is not full and can be loaded with a char...

Page 377: ...iver status When written to these bits control the meaning of UISRn RxFIFO 00 Inhibit receiver FIFO status indication in UISRn 01 Receiver FIFO 25 full 10 Receiver FIFO 50 full 11 Receiver FIFO 75 full When read these bits indicate the emptiness level of the FIFO 00 Receiver FIFO 25 full 01 Receiver FIFO 25 full 10 Receiver FIFO 50 full 11 Receiver FIFO 75 full 5 FULL Receiver FIFO full 0 Receiver...

Page 378: ... 16 13 UIPn Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 CTS CTS state The CTS value is latched and reflects the state of the input pin when UIPn is read Note This bit has the same function and value as UIPCRn RTS 0 The current state of the CTS input is logic 0 1 The current state of the CTS input is logic 1 7 1 0 Field RTS Reset 0000_0000 R W Write only Addr UART0 MBA...

Page 379: ...ive independent of the voltage level negated indicates that a signal is inactive Table 16 15 UART Module Signals Signal Description Transmitter Serial Data Output URT_TxD URT_TxD is held high mark condition when the transmitter is disabled idle or operating in the local loop back mode Data is shifted out on URT_TxD on the falling edge of the clock source with the least significant bit lsb sent fir...

Page 380: ...T_CLK provides a synchronous clock mode when divided by 16 it is asynchronous CLKIN supplies an asynchronous clock source that is prescaled by 32 and then divided by the 16 bit value programmed in UDUn and UDLn See Section 16 3 11 UART Divider Upper Lower Registers UDUn UDLn The precision of this clock source can be tuned using the 4 bit value programmed in UFPDn Request to Send URT_RTS This outpu...

Page 381: ...clocking source it goes through a divide by 32 prescaler and then passes through the 16 bit divider of the concatenated UDUn and UDLn registers The UFPD register can be used to improve the accuracy of the clock source as shown in the following example using a 48 MHz CLKIN and 230kbs UART baud rate 1 UART Divider CLKIN 16 x 2 x UART Baud Rate 48E06 32 x 230E03 6 52 6 truncate to lowest whole number...

Page 382: ...n effects from the external drivers If the calculated rate is inaccurate UDUn UDLn and UFPDn must be written with the appropriate value as soon as possible to ensure that characters are properly received by the UART The first character is always correctly captured even though the transmission rate is not yet calculated The first character must be an odd character such as a or A to ensure that it c...

Page 383: ...ansmitter output on the falling edge of the clock source After the stop bits are sent if no new character is in the transmitter holding register the TxD output remains high mark condition and the transmitter empty bit USRn TxEMP is set Transmission resumes and TxEMP is cleared when the CPU loads a new character into the UART transmitter buffer UTBn If the transmitter receives a disable command it ...

Page 384: ...nd RTS is appropriately programmed RTS is negated one bit time after the character in the shift register is completely transmitted The transmitter must be manually reenabled by reasserting RTS before the next message is to be sent The transmitter must be enabled prior to accepting a START BREAK command If the transmitter is disabled while the BREAK is active the BREAK is not terminated The BREAK c...

Page 385: ...e of the programmed clock source The lsb is received first The data is then transferred to a receiver holding register and USRn RxRDY is set If the character is less than eight bits the most significant unused bits in the receiver holding register are cleared After the stop bit is detected the receiver immediately looks for the next start bit However if a non zero character is received without a s...

Page 386: ...ver shift register and loaded into the top empty receiver holding register position of the FIFO Similar to the transmitter several status bits and interrupts provide visibility into the status of the FIFO In addition to the data byte three status bits parity error PE framing error FE and received break RB are appended to each data character in the FIFO OE overrun error is not appended By programmi...

Page 387: ...ver detects the start bit of the new overrunning character Visibility into the status of the FIFO is provided by various bits and interrupts as shown in Table 16 17 To support flow control the receiver can be programmed to automatically negate and assert RTS in which case the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full The receiver asserts RTS w...

Page 388: ... transmitter is inactive USRn TxEMP TxRDY are inactive and data is sent as it is received Received parity is checked but is not recalculated for transmission Character framing is also checked but stop bits are sent as they are received A received break is echoed as received until the next valid start bit is detected Autobaud operation does not affect automatic echo mode that is the first character...

Page 389: ... or multiprocessor applications In this mode a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations Although slave stations have their channel receivers disabled they continuously monitor the master s data stream When the master sends an address character the slave receiver channel notifies its respective CPU by setting USRn R...

Page 390: ... is zero data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register stack during read operations In either case the data bits are loaded into the data portion of the stack while the A D bit is loaded into the status portion of the stack normally used for a parity error USRn PE Detection of breaks and framing or overrun errors operat...

Page 391: ...2 Before SINIT is called at system initialization the calling routine allocates 2 words on the system stack On return to the calling routine SINIT passes UART status data on the stack If SINIT finds no errors the transmitter and receiver are enabled SINIT calls CHCHK to perform the checks When called SINIT places the UART in local loop back mode and checks for the following errors Transmitter neve...

Page 392: ...or byte operations but only data byte D 7 0 is valid Figure 16 31 shows the UART module initialization sequence Figure 16 31 UART Mode Programming Flowchart Sheet 1 of 5 SERIAL MODULE INITIATE CHANNEL INTERRUPTS SAVE CHANNEL STATUS ANY ERRORS ENABLE RECEIVER ASSERT REQUEST TO SEND RETURN SINIT CHK1 ENABLA Y N SINITR CALL CHCHK ENABLE ...

Page 393: ... N CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD IS TRANSMITTER READY WAITED TOO LONG WAITED TOO LONG N Y SEND CHARACTER TO TRANSMITTER HAS CHARACTER BEEN RECEIVED CHCHK TxCHK SNDCHR RxCHK N Y N SET TRANSMITTER NEVER READY FLAG SET RECEIVER NEVER READY FLAG A B Y Y N ...

Page 394: ...rt Sheet 3 of 5 B Y N N A Y A B Y N RETURN HAVE FRAMING ERROR SET FRAMING ERROR FLAG HAVE PARITY ERROR SET PARITY ERROR FLAG GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER SET INCORRECT CHARACTER FLAG DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE FRCHK RSTCHN PRCHK CHRCHK ...

Page 395: ... BREAK CLEAR CHANGE IN BREAK STATUS BIT HAS END OF BREAK IRQ ARRIVED YET CLEAR CHANGE IN BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS RTE SIRQR N Y N DOES CHANNEL A RECEIVER HAVE A CHARACTER PLACE CHARACTER IN D0 N Y ABRKI1 ABRKI Y INCH RETURN SIRQ ...

Page 396: ...16 36 MCF5272 User s Manual Operation Figure 16 31 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH N Y IS TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN ...

Page 397: ...e corresponding port direction registers are programmed The general purpose I O signals are configured as three ports each having up to 16 signals These three general purpose I O ports are shared with other signals as follows Control registers for each port select the function GPIO or peripheral pin assigned to each pin Pins can have as many as four functions including GPIO There is no configurati...

Page 398: ...ntrol register is used to configure pins that have multiple functions 0b01 through 0b11 but no GPIO function CAUTION Do not attempt to program a pin function that is not defined Where no function is defined the function code is labeled Reserved and is considered invalid Programming any control register field with a reserved value has an unpredictable effect on the corresponding pin s operation Res...

Page 399: ...000 R W Read Write Addr MBAR 0x0080 Figure 17 1 Port A Control Register PACNT Table 17 3 PACNT Field Descriptions Bits Name Description 31 30 PACNT15 Configure pin M3 If this pin is programmed to function as INT6 it is not available as a GPIO 00 PA15 01 DGNT1 1x Reserved 29 28 PACNT14 Configure pin M2 00 PA14 01 DREQ1 1x Reserved 27 26 PACNT13 Configure pin L3 00 PA13 01 DFSC3 1x Reserved 25 24 PA...

Page 400: ...ved 13 12 PACNT6 Configure pin E1 00 PA6 01 USB_RxD 1x Reserved 11 10 PACNT5 Configure pin E2 00 PA5 01 USB_TxEN 1x Reserved 9 8 PACNT4 Configure pin E3 00 PA4 01 USB_Susp 1x Reserved 7 6 PACNT3 Configure pin E4 00 PA3 01 USB_TN 1x Reserved 5 4 PACNT2 Configure pin E5 00 PA2 01 USB_RN 1x Reserved 3 2 PACNT1 Configure pin D1 00 PA1 01 USB_RP 1x Reserved 1 0 PACNT0 Configure pin D2 00 PA0 01 USB_TP ...

Page 401: ... QSPI_CS1 L2 PA12 DFSC2 L3 PA13 DFSC3 M2 PA14 DREQ1 M3 PA15 DGNT11 1 If this pin is programmed to function as INT6 it is not avaiable as a GPIO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field PBCNT15 PBCNT14 PBCNT13 PBCNT12 PBCNT11 PBCNT10 PBCNT9 PBCNT8 Reset 0000_0000_0000_0000 R W Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PBCNT7 PBCNT6 PBCNT5 PBCNT4 PBCNT3 PBCNT2 PBCNT1 PBCNT0...

Page 402: ...9 00 PB12 01 E_RxD2 1x Reserved 23 22 PBCNT11 Configure pin P9 00 PB11 01 E_RxD3 10 QSPI_CS1 11 Reserved 21 20 PBCNT10 Configure pin L8 00 PB10 01 E_TxD1 1x Reserved 19 18 PBCNT9 Configure pin M8 00 PB9 01 E_TxD2 1x Reserved 17 16 PBCNT8 Configure pin N8 00 PB8 01 E_TxD3 1x Reserved 15 14 PBCNT7 Configure pin M6 00 PB7 01 TOUT0 1x Reserved 13 12 PBCNT6 Configure pin G4 00 PB6 01 Reserved 1x Reserv...

Page 403: ...o TIN3 00 PB1 01 URT0_RxD TIN3 1x Reserved 1 0 PBCNT0 Configure pin H4 00 PB0 01 URT0_TxD 1x Reserved Table 17 6 Port B Control Register Function Bits Pin Number PBCNTxx 00 Function 0b00 PBCNTxx 01 Function 0b01 PBCNTxx 10 Function 0b10 PBCNTxx 11 Function 0b11 H4 PB0 URT0_TxD H1 PB1 URT0_RxD TIN3 H2 PB2 URT0_CTS H3 PB3 URT0_RTS G3 PB4 URT0_CLK F3 PB5 TA G4 PB6 M6 PB7 TOUT0 N8 PB8 E_TxD3 M8 PB9 E_...

Page 404: ...bility Port D has no data register nor data direction register Table 17 7 describes PDCNT fields Table 17 8 provides the same information organized by function 31 16 Field Reset R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PDCNT7 PDCNT6 PDCNT5 PDCNT4 PDCNT3 PDCNT2 PDCNT1 PDCNT0 Reset 0000_0000_0000_0000 R W Read Write Addr MBAR 0x0098 Figure 17 3 Port D Control Register PDCNT Table 17 7 PDCNT F...

Page 405: ... 10 URT1_CTS 11 QSPI_CS2 3 2 PDCNT1 Configure pin K1 The signal URT1_RxD is always internally connected to TIN4 00 High impedance 01 DIN0 10 URT1_RxD TIN4 11 Reserved 1 0 PDCNT0 Configure pin J4 00 High impedance 01 DCL0 10 URT1_CLK 11 Reserved Table 17 8 Port D Control Register Function Bits PIN Number PDCNTxx 00 Function 0b00 PDCNTxx 01 Function 0b01 PDCNTxx 10 Function 0b10 PDCNTxx 11 Function ...

Page 406: ...PADDR The control bits in all three registers operate in the same manner 17 3 1 Port A Data Direction Register PADDR The PADDR determines the signal direction of each parallel port pin programmed as a GPIO port in the PACNT 17 3 2 Port B Data Direction Register PBDDR The PBDDR determines the signal direction of each parallel port pin programmed as a GPIO port in the PBCNT 15 0 Field PADDR Reset 00...

Page 407: ...After a system reset these register bits are all cleared When any port lines are configured as outputs a logic zero appears on those pins unless the data register is written with an initial data value prior to setting the pin direction The reset values given in the following register diagrams are the port output values written to the registers during reset and do not reflect the value of a registe...

Page 408: ...lue for inputs corresponds to the logic level at the pin for outputs the value corresponds to the logic level driven onto the pin Note that PxDAT has no effect on pins which have not been configured for GPIO 15 0 Field PxDAT Reset Undefined R W Read Write Addr MBAR 0x0086 PADAT 0x008E PBDAT 0x0096 PCDAT Figure 17 7 Port x Data Register PADAT PBDAT and PCDAT ...

Page 409: ...ing model and timing diagram 18 1 Overview The PWM module shown in Figure 18 1 generates a synchronous series of pulses having programmable duty cycle With a suitable low pass filter the PWM can be used as a digital to analog converter Figure 18 1 PWM Block Diagram 3 Identical Modules PWM_OUT2 PWM_OUT1 PWM_OUT0 SYS CLOCK PRESCALER COUNTER CONTROL REG WIDTH REG WIDTH BUFFER PWCR CKSL EN Internal Bu...

Page 410: ...ecting the current cycle At the beginning of each period the value of the width buffer register is loaded into the width register which feeds the comparator This value is used for comparison during the next cycle The prescaler contains a variable divider that can reduce the incoming clock frequency by certain values between 1 and 32768 18 3 PWM Programming Model This section describes the register...

Page 411: ...EN Enable 0 Disables the PWM While disabled the PWM is in low power mode and the prescaler does not count When the PWM is disabled the output is forced to the value of PWCRn LVL 1 Enables the PWM 6 FRC1 Force output high 0 Default reset value PWM functions normally 1 The PWM drives the output high for the entire counter period PWCRn FRC1 has a lower priority than PWCRn EN so setting PWCRn FRC1 whi...

Page 412: ... end of the current output cycle That is the width value is not modified until after the counter has wrapped around The PWM must be disabled and then re enabled to affect its operation before the end of the current output cycle Figure 18 3 PWM Width Register PWWDn Figure 18 4 shows example PWM waveforms and their dependence on PWWD PW 7 0 Field PW Reset 0000_0000 R W R W Address MBAR 0x0D0 PWWD0 0...

Page 413: ...8 5 PWM Programming Model Figure 18 4 PWM Waveform Examples PWCRn EN 1 256T T 128T 255T T 128T 255T PWWD PW 0x00 PWWD PW 0x01 PWWD PW 0x80 PWWD PW 0xFF PWCRn CKSL 0000 T 1 x CPU clock period PWCRn CKSL 1111 T 32768 x CPU clock period PWCRn FRC1 1 ...

Page 414: ...18 6 MCF5272 User s Manual PWM Programming Model ...

Page 415: ...efault to inputs after reset Table 19 2 presents the same information sorted by pin number instead of signal function NOTE In this manual the term asserted indicates the active signal state negated indicates inactive Names of active low signals are given overbars for example INT1 and SDWE Table 19 1 Signal Descriptions Sorted by Function Configured by see notes Pin Functions Description Map BGA Pi...

Page 416: ...t A5 C12 O 7 50 A8 SDA7 SDA6 A8 SDRAM 16bit A7 SDRAM 32bit A6 C13 O 7 50 A9 SDA8 SDA7 A9 SDRAM 16bit A8 SDRAM 32bit A7 C14 O 7 50 BS0 Byte strobe 0 A9 O 4 50 BS1 Byte strobe 1 C8 O 4 50 BS2 Byte strobe 2 E12 O 4 50 BS3 Byte strobe 3 E13 O 4 50 CAS0 SDRAM column select strobe C9 O 11 50 CLKIN CPU external clock input M14 I BUSW 1 0 CS0 Boot Chip select 0 K9 O 2 30 CS1 Chip select 1 K10 O 2 30 CS2 C...

Page 417: ...O 4 30 WSEL pin D22 D6 D22 D6 A8 I O 4 30 WSEL pin D23 D7 D23 D7 B8 I O 4 30 WSEL pin D24 D8 D24 D8 F12 I O 4 30 WSEL pin D25 D9 D25 D9 F13 I O 4 30 WSEL pin D26 D10 D26 D10 F14 I O 4 30 WSEL pin D27 D11 D27 D11 G12 I O 4 30 WSEL pin D28 D12 D28 D12 G13 I O 4 30 WSEL pin D29 D13 D29 D13 G14 I O 4 30 WSEL pin D3 PC3 D3 port C bit 3 K11 I O 4 30 WSEL pin D30 D14 D30 D14 H14 I O 4 30 WSEL pin D31 D15...

Page 418: ...0 I O 2 E_RxCLK Ethernet Rx clock N7 I E_RxD0 Ethernet Rx data P7 I E_RxDV Ethernet Rx data valid M7 I E_Tx CLK Ethernet Tx clock L7 I E_TxD0 Ethernet Tx data N6 O 4 30 E_TxEN Ethernet Tx enable P8 O 2 30 E_TxER Transmit error 100 base T Ethernet only M10 O 2 30 FSC1 FSR1 DFSC1 PLIC port 1 IDL FSR GCI FSC1 Generated frame sync 1 Out L4 I O 2 30 GND Ground E 7 8 F 7 8 G 6 9 H 6 9 J 7 8 Port D Cntl ...

Page 419: ... 4 50 Port A Cntl Reg PA0 USB_TP Port A bit 0 USB Tx positive D2 I O 2 20 Port A Cntl Reg PA1 USB_RP Port A bit 1 USB Rx positive D1 I O 2 20 Port A Cntl Reg PA10 DREQ0 Port A bit 10 IDL DREQ0 K5 I O 2 30 Port A Cntl Reg PA11 QSPI_CS1 Port A bit 11 QSPI chip select 1 L1 I O 2 30 Port A Cntl Reg PA12 DFSC2 Port A bit 12 Delayed frame sync 2 L2 I O 2 30 Port A Cntl Reg PA13 DFSC3 Port A bit 13 Delay...

Page 420: ...et only L8 I O 4 30 Port B Cntl Reg PB11 E_RxD3 Port B bit 11 Rx data bit 3 100 Base T Ethernet only P9 I O 2 30 Port B Cntl Reg PB12 E_RxD2 Port B bit 12 Rx data bit 2 100 Base T Ethernet only N9 I O 2 30 Port B Cntl Reg PB13 E_RxD1 Port B bit 13 Rx data bit 1 100 Base T Ethernet only M9 I O 2 30 Port B Cntl Reg PB14 E_RxER Port B bit 14 Receive Error 100 Base T Ethernet only L9 I O 2 30 Port B C...

Page 421: ...QSPI_CLK BUSW1 QSPI serial clock CS0 bus width bit 1 L5 O 4 30 QSPI_CS0 BUSW0 QSPI peripheral chip select 0 CS0 bus width bit 0 M5 O 2 30 QSPI_Din QSPI data input P4 I QSPI_Dout WSEL QSPI data output Bus width selection N4 O 4 30 R W Read Write P14 O 11 50 RAS0 SDRAM row select strobe A10 O 11 50 RSTI Device reset M12 I RSTO Reset output strobe F4 O 2 20 SDBA0 SDRAM bank 0 select J14 O 11 50 SDBA1...

Page 422: ...4 30 MTMOD TCK PSTCLK JTAG test clock in BDM PSTCLK output C4 I O 11 30 MTMOD TDI DSI JTAG test data in BDM data in A4 I MTMOD TDO DSO JTAG test data out BDM data out D5 O 4 30 TEA BDM debug transfer error acknowledge A3 I TEST Device test mode enable E6 I TIN0 Timer 0 input L6 I MTMOD TMS BKPT JTAG test mode BDM select breakpoint input B4 I MTMOD TRST DSCLK JTAG reset BDM clock D4 I USB_CLK USB e...

Page 423: ... 16bit A12 SDRAM 32bit A11 O A12 A2 SDA1 SDA0 A2 SDA1 SDA0 A2 SDRAM 16bit A1 SDRAM 32bit A0 O A13 A3 SDA2 SDA1 A3 SDA2 SDA1 A3 SDRAM 16bit A2 SDRAM 32bit A1 O A14 A4 SDA3 SDA2 A4 SDA3 SDA2 A4 SDRAM 16bit A3 SDRAM 32bit A2 O B1 PST0 PST0 Internal processor status 0 O B2 DDATA2 DDATA2 Debug data 2 O B3 MTMOD MTMOD 0 selects JTAG mode 1 selects BDM mode I B4 TMS BKPT TMS BKPT JTAG test mode BDM selec...

Page 424: ...SDRAM 32bit A9 O C12 A7 SDA6 SDA5 A7 SDA6 SDA5 A7 SDRAM 16bit A6 SDRAM 32bit A5 O C13 A8 SDA7 SDA6 A8 SDA7 SDA6 A8 SDRAM 16bit A7 SDRAM 32bit A6 O C14 A9 SDA8 SDA7 A9 SDA8 SDA7 A9 SDRAM 16bit A8 SDRAM 32bit A7 O D1 PA1 USB_RP PA1 USB_RP Port A bit 1 USB Rx positive I O D2 PA0 USB_TP PA0 USB_TP Port A bit 0 USB Tx positive I O D3 PST3 PST3 Internal processor status 3 O D4 TRST DSCLK TRST DSCLK JTAG...

Page 425: ...USB Rx negative I O E6 TEST TEST Device test mode enable I E7 GND Ground GND E8 GND Ground GND E9 A22 A22 A22 O E10 D15 PC15 D15 PC15 D15 port C bit 15 I O E11 D13 PC13 D13 PC13 D13 port C bit 13 I O E12 BS2 BS2 Byte strobe 2 O E13 BS3 BS3 Byte strobe 3 O E14 SDCLK SDCLK SDRAM bus clock Same frequency as CPU clock O F1 USB_D USB_D USB line driver high analog O F2 USB_D USB_D USB line driver low an...

Page 426: ... PC11 D11 PC11 D11 port C bit 11 I O G12 D27 D11 D27 D11 D27 D11 I O G13 D28 D12 D28 D12 D28 D12 I O G14 D29 D13 D29 D13 D29 D13 I O H1 PB1 URT0_RxD PB1 URT0_RxD Port B bit 1 UART0 Rx data I O H2 PB2 URT0_ CTS PB2 URT0_CTS Port B bit 2 UART0 CTS I O H3 PB3 URT0_ RTS PB3 URT0_RTS Port B bit 3 UART0 RTS I O H4 PB0 URT0_TxD PB0 URT0_TxD Port B bit 0 UART0 Tx data I O H5 VDD 3 3V VDD H6 GND Ground GND...

Page 427: ...J14 SDBA0 SDBA0 SDRAM bank 0 select O K1 High Z DIN0 URT1_RxD DIN0 URT1_RxD IDL GCI data in UART1 Rx data I K2 High Z URT1_ CTS QSPI_ CS2 URT1_CTS QSPI_CS2 UART1 CTS QSPI_CS2 I O K3 High Z URT1_RTS INT5 URT1_RTS INT5 UART1 RTS INT5 I O K4 High Z DOUT0 URT1_TxD DOUT0 URT1_TxD IDL GCI data Out UART1 Tx data O K5 PA10 DREQ0 PA10 DREQ0 Port A bit 10 IDL DREQ0 I O K6 High Z PWM_ OUT2 TIN1 PWM_OUT2 TIN1...

Page 428: ...ve Error 100 Base T Ethernet only I O L10 E_CRS E_CRS Carrier sense 100 base T Ethernet only I L11 CS5 CS5 Chip select 5 O L12 D0 PC0 D0 PC0 D0 port C bit 0 I O L13 D1 PC1 D1 PC1 D1 port C bit 1 I O L14 D2 PC2 D2 PC2 D2 port C bit 2 I O M1 DCL1 GDCL1_OUT DCL1 GDCL1_OUT PLIC ports 1 2 3 data clock Generated DCL out I O M2 PA14 DREQ1 PA14 DREQ1 Port A bit 14 PLIC port 1 IDL D channel request I O M3 ...

Page 429: ...s 1 2 3 data input I N3 INT3 INT3 Interrupt input 3 I N4 QSPI_Dout WSEL QSPI_Dout WSEL QSPI data output Bus width selection O N5 PWM_OUT0 PWM_OUT0 PWM output compare 0 O N6 E_TxD0 E_TxD0 Ethernet Tx data O N7 E_RxCLK E_RxCLK Ethernet Rx clock I N8 PB8 E_TxD3 PB8 E_TxD3 Port B bit 8 Tx data bit 3 100 Base T Ethernet only I O N9 PB12 E_RxD2 PB12 E_RxD2 Port B bit 12 Rx data bit 2 100 Base T Ethernet...

Page 430: ... data to and from the MCF5272 A read or write operation can transfer 8 16 or 32 bits in one bus cycle P1 PA7 QSPI_CS3 DOUT3 PA7 QSPI_CS3 DOUT3 PA7 QSPI chip select 4 PLIC port 3 data output I O P2 High Z DIN3 INT4 DIN3 INT4 Interrupt 4 input PLIC port 3 data input I P3 INT2 INT2 Interrupt input 1 I P4 QSPI_Din QSPI_Din QSPI data input I P5 High Z PWM_ OUT1 TOUT1 PWM_OUT1 TOUT1 PWM output compare 1...

Page 431: ...F5272 to interface directly to SRAM EPROM EEPROM and external memory mapped peripherals These signals can be programmed for an address location with masking capabilities port size burst capability indication and wait state generation CS0 provides a special function as a global chip select that allows access to boot ROM at at reset CS0 can have its address redefined after reset CS0 is the only chip...

Page 432: ...s For SDRAM devices BS 3 0 should be connected to individual SDRAM DQM signals Note that most SDRAMs associate DQM3 with the MSB in which case BS3 should be connected to the SDRAM s DQM3 input NOTE In 16 bit bus mode longword accesses are performed as two sequential word accesses Table 19 5 shows how BS 3 0 should be connected to DQMx for 16 and 32 bit SDRAM configurations Table 19 3 Byte Strobe O...

Page 433: ...pin requires a 4 7 KΩ pull up resistor or external logic that drives inactive high TA must always be returned high before it can be detected again Asserting TA into the next bus cycle has no effect and does not terminate the bus cycle NOTE Even though EBI modes set to SDRAM require setting the wait state field in the chip select option register to 31 a low signal should never be applied to TA duri...

Page 434: ...DRAM write enable 19 5 11 SDRAM Clock Enable SDCLKE This output is the SDRAM clock enable 19 5 12 SDRAM Bank Selects SDBA 1 0 These outputs are the SDRAM bank select signals 19 5 13 SDRAM Row Address 10 A10 A10 Precharge A10_PRECHG This output is the SDRAM row address 10 and the precharge strobe 19 6 CPU Clock and Reset Signals This section describes clock and reset signals in the CPU 19 6 1 RSTI ...

Page 435: ... is driven low for 32K CPU clocks when the software watchdog timer times out or when a low input level is applied to RSTI 19 7 Interrupt Request Inputs INT 6 1 The six interrupt request inputs INT 6 1 can generate separate maskable interrupts on negative edge high to low or positive edge low to high transitions In addition to the triggering edge being programmable the priority can also be programm...

Page 436: ...this section for data and clock signals These signals are multiplexed with the GPIO port B signals PB 4 0 19 9 1 Transmit Serial Data Output URT0_TxD PB0 UART0 mode URT0_TxD is the transmitter serial data output for the UART0 module The output is held high mark condition when the transmitter is disabled idle or in the local loopback mode Data is shifted out lsb first on this pin at the falling edg...

Page 437: ...tiplexed with the GPIO port A signals PA 6 0 19 10 1 USB Transmit Serial Data Output USB_TP PA0 USB mode USB_TP is the non inverted data transmit output Port A mode This pin can also be configured as the PA0 I O 19 10 2 USB Receive Serial Data Input USB_RP PA1 USB mode USB_RP is the non inverted receive data input Port A mode This pin can also be configured as the PA1 I O 19 10 3 USB Receive Data ...

Page 438: ...odule When this pin is tied to GND or VDD the USB module automatically uses the internal CPU clock In this case the CLKIN must be 48 MHz if the system is to use the USB function 19 10 10 INT1 USB Wake on Ring USB_WOR The USB module allows for INT1 to generate the USB wake on ring signal to the USB host controller This function is enabled by a control bit in the USB module WOR is provided to allow ...

Page 439: ...ither clock the event counter or provide a trigger to the timer value capture logic PWM mode Pulse width modulator 2 PWM_OUT2 compare output 19 11 4 Timer Output 1 TOUT1 PWM Mode Output 1 PWM_OUT1 Timer mode Timer output TOUT1 is the output from timer 1 PWM mode Pulse width modulator 1 PWM_OUT1 compare output 19 12 Ethernet Module Signals The following signals are used by the Ethernet module for d...

Page 440: ...rom the PHY to the media access controller when E_RxDV is asserted This signal is used for 10 Mbps Ethernet data This signal is also used for MII mode Ethernet data in conjunction with E_RxD 3 1 19 12 7 Transmit Enable E_TxEN The transmit enable E_TxEN output indicates when valid nibbles are present on the MII This signal is asserted with the first nibble of a preamble and is negated before the fi...

Page 441: ...rmation between the external PHY and the media access controller Data is synchronous to E_MDC Applies to MII mode operation This signal is an input after reset When the FEC is operated in 10Mbps 7 wire interface mode this signal should be connected to Vss 19 12 13 Transmit Error E_TxER Ethernet mode When the E_TxER output is asserted for one or more clock cycles while E_TxEN is also asserted the P...

Page 442: ...sampled on the rising or falling edge of QSPI_CLK Each byte is written to RAM lsb first 19 14 3 QSPI Serial Clock QSPI_CLK BUSW1 The QSPI serial clock QSPI_CLK BUSW1 provides the serial clock from the QSPI The polarity and phase of QSPI_CLK are programmable The output frequency is programmed according to the following formula in which n can be any value between 1 and 255 QSPI_CLK CLKIN 2 n At rese...

Page 443: ...ured to use a dedicated pin set Ports 1 2 and 3 always share the same data clock DCL 19 15 1 GCI IDL TDM Port 0 This section describes signals used by the PLIC module port 0 interface 19 15 1 1 Frame Sync FSR0 FSC0 PA8 IDL mode FSR0 is an input for the 8 KHz frame sync for port 0 GCI mode FSC0 is an input for the 8 KHz frame sync for port 0 It is active high in this mode Normally the GCI FSC signa...

Page 444: ...is stopped for power down mode any transition on this pin restarts it 19 15 1 5 UART1 CTS URT1_CTS QSPI_CS2 UART1 URT1_CTS is the clear to send input indicating to the UART1 module that it can begin data transmission QSPI mode This output pin provides a QSPI peripheral chip select QSPI_CS2 when in Master mode QSPI_CS2 can be programmed to be active high or low 19 15 1 6 UART1 RTS URT1_RTS INT5 Int...

Page 445: ...ut of DOUT1 on the rising edge of DCL1 GCI mode GDCL1_OUT is used to clock data in and out of DIN1 and DOUT1 for GCI port 1 DCL1 is twice the bit rate that is two clocks per data bit When this pin is configured as an output the GDCL1_OUT clock signal from the on chip synthesizer clock generator is output on this pin Also GDCL1_OUT is used to internally drive all ports and delayed sync generators a...

Page 446: ...e for signalling to a layer 1 S T transceiver that a frame of data is ready to be sent on the port 1 D channel Port A mode I O pin PA14 19 15 2 6 D Channel Grant DGNT1_INT6 PA15_INT6 This pin can be independently configured as the input DGNT1 used by a Layer one ISDN S T transceiver to indicate that D channel access has been granted Port A mode I O pin PA15 Special interrupt mode The INT6 interrup...

Page 447: ...mode I O pin PA13 19 15 3 3 QSPI_CS3 Port 3 GCI IDL Data Out 3 PA7 PA7 DOUT3 QSPI_CS3 QSPI mode The QSPI chip select QSPI_CS3 is the default configuration after device reset IDL mode This pin can be configured as a dedicated output for clocking data out of IDL port 3 Data is clocked out of DOUT3 on the rising edge of DCL1 After device reset port 3 is connected to DOUT1 by setting a bit in the PLIC...

Page 448: ...input provides a clock for on board test logic defined by the IEEE 1149 1 standard TCK should be grounded if the JTAG port is not used and MTMOD is tied low BDM mode PSTCLK is an output at the same frequency as the CPU clock It is used for indicating valid processor status data on the PST and DDATA pins 19 16 2 Test Mode Select and Force Breakpoint TMS BKPT JTAG mode The TMS input controls test mo...

Page 449: ...igh BDM mode is enabled 19 16 7 Debug Transfer Error Acknowledge TEA An external slave asserts the TEA input to indicate an error condition for the current bus transfer It is provided to allow full debug port capability The assertion of TEA causes the MCF5272 to abort the current bus cycle If a 10 KΩ pullup resistor is not connected external logic must drive TEA high when it is inactive TEA has no...

Page 450: ...mode signal and should never have a pull down resistor The remaining three mode select signals must each have a 4 7 KΩ pull up or pull down resistor 0111 Begin execution of RTE instruction 1000 Begin 1 byte transfer on DDATA 1001 Begin 2 byte transfer on DDATA 1010 Begin 3 byte transfer on DDATA 1011 Begin 4 byte transfer on DDATA 1100 1 Exception processing 1101 1 Emulator mode entry exception pr...

Page 451: ...s is dedicated to the on chip USB transceiver 1 0 16 bits 1 1 Reserved do not use Table 19 9 MCF5272 High Impedance Mode Selection HI Z Data Bus Width 0 Enable HI Z mode all pins are high impedance 1 Normal operation Table 19 8 MCF5272 CS0 Memory Bus Width Selection Continued BUSW1 BUSW0 CS0 Bus Width ...

Page 452: ...19 38 MCF5272 User s Manual Power Supply Pins ...

Page 453: ...port external bus masters The MCF5272 has three on chip bus masters the CPU the Ethernet controller and the memory to memory DMA controller 20 1 Features The following list summarizes the key bus operation features 23 bits of address and 32 bits of data Device physical data bus width configurable for 16 or 32 bits Accesses 8 16 and 32 bit port sizes Generates byte word longword and line size trans...

Page 454: ...16 bits of the data bus regardless of the chip select port width and operand size 20 2 3 Read Write R W This output signal defines the data transfer direction for the current bus cycle A high logic one level indicates a read cycle a low logic zero level indicates a write cycle During SDRAM bus cycles R W is driven high When the CPU is in SLEEP or STOP modes this signal is driven high NOTE Use the ...

Page 455: ...e TA This active low synchronous input signal indicates the successful completion of a requested data transfer operation During MCF5272 initiated transfers transfer acknowledge TA is an asynchronous input signal from the referenced slave device indicating completion of the transfer ...

Page 456: ...ughout the transfer TA is not used for termination during SDRAM accesses 20 2 5 Transfer Error Acknowledge TEA An external slave asserts this active low input signal to abort a transfer The assertion of TEA immediately aborts the bus cycle The assertion of TEA has precedence over the assertion of TA The MCF5272 edge detects and retimes the TEA input TEA is an asynchronous input signal The TEA sign...

Page 457: ...SDWE A10_PRECHG SDCLKE and CS7 SDCS The asynchronous INT 6 1 signals are internally synchronized to resolve the input to a valid level before being used 20 5 Data Transfer Mechanism The MCF5272 supports byte word and longword operands and allows accesses to 8 16 and 32 bit data ports The MCF5272 supports port sizes of the specific memory enables internal generation of transfer termination and sets...

Page 458: ...equirement ensures that the MCF5272 correctly transfers valid data to 8 16 and 32 bit ports The bytes of operands are designated as shown in Figure 20 1 The most significant byte of a longword operand is OP0 OP3 is the least significant byte The two bytes of a word length operand are OP2 most significant and OP3 The single byte of a byte length operand is OP3 These designations are used in the fig...

Page 459: ...bytes Table 20 3 describes data bus byte strobes Note that most SDRAMs associate DQM3 with the MSB thus BS3 should be connected to the SDRAM s DQM3 input Table 20 3 Data Bus Byte Strobes Transfer Size Port Size A 1 0 BS3 BS2 BS1 BS0 D 31 24 D 23 16 D 15 8 D 7 0 Byte 8 bit not supported for SDRAM 00 0 1 1 1 01 0 1 1 1 10 0 1 1 1 11 0 1 1 1 16 bit 00 0 1 1 1 01 1 0 1 1 10 0 1 1 1 11 1 0 1 1 32 bit 0...

Page 460: ...d are not required during that read cycle Bytes labeled are not valid transfers Word 8 bit not supported for SDRAM 00 0 1 1 1 01 0 1 1 1 10 0 1 1 1 11 0 1 1 1 16 bit 00 0 0 1 1 10 0 0 1 1 32 bit 00 0 0 1 1 10 1 1 0 0 Longword 8 bit not supported for SDRAM 00 0 1 1 1 01 0 1 1 1 10 0 1 1 1 11 0 1 1 1 16 bit 00 0 0 1 1 10 0 0 1 1 32 bit 00 0 0 0 0 Line 8 bit not supported for SDRAM 00 0 1 1 1 01 0 1 ...

Page 461: ...Required 32 Bit Port 16 Bit Port 8 Bit Port D 31 24 D 23 16 D 15 8 D 7 0 D 31 24 D 23 16 D 31 24 Byte 00 Byte 0 X X X Byte 0 X Byte 0 01 X Byte 1 X X X Byte 1 Byte 1 10 X X Byte 2 X Byte 2 X Byte 2 11 X X X Byte 3 X Byte 3 Byte 3 Word 00 Byte 0 Byte 1 X X Byte 0 Byte 1 Byte 0 01 Byte 1 10 X X Byte2 Byte 3 Byte 2 Byte 3 Byte 2 11 Byte 3 Longword 00 Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 Byte 1 Byte 0 0...

Page 462: ...SORn WS is 0x1F When TA is used to terminate the bus cycle the bus cycle will have a minimum of one wait states Additional wait states can be added by delaying the assertion of TA Longword 00 OP0 OP1 OP2 OP3 01 OP1 X X X 10 OP2 OP3 X X 11 OP3 X X X Line 00 OP0 OP1 OP2 OP3 01 OP1 X X X 10 OP2 OP3 X X 11 OP3 X X X Table 20 6 External Bus Interface Codes for CSBRs A0 CSBRn EBI Applicable Chip Select ...

Page 463: ... 20 11 External Bus Interface Types Figure 20 3 Longword Read EBI 00 32 Bit Port Internal Termination NOTE Wait states if needed are added immediately after C2 in Figure 20 3 CLKIN A 22 0 D 31 0 OE BS 3 0 R W CSn C1 C2 H H TA ...

Page 464: ...ure 20 4 Word Write EBI 00 16 32 Bit Port Internal Termination Figure 20 5 Longword Read with Address Setup EBI 00 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 3 2 C1 C2 BS 1 0 TA H H H CLKIN A 22 0 D 31 0 OE BS 3 0 R W CSn TA C1 C2 C3 H H ...

Page 465: ...0 6 Longword Write with Address Setup EBI 00 32 Bit Port Internal Termination Figure 20 7 Longword Read with Address Hold EBI 00 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H CLKIN A 22 0 D 31 0 OE BS 3 0 R W CSn TA C1 C2 C3 H H ...

Page 466: ...20 8 Longword Write with Address Hold EBI 00 32 Bit Port Internal Termination Figure 20 9 Longword Read EBI 00 32 Bit Port Terminated by TA with One Wait State CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 CW C3 ...

Page 467: ...key difference between EBI 11 and EBI 00 is that BS 3 0 can be directly connected to the R W inputs of the 8 bit wide SRAM devices and the R W output from the MCF5272 can be left unconnected The number of wait states required for the external memory or peripheral can be programmed in CSORn WS The external transfer acknowledge signal TA is provided to allow off chip control of wait states External ...

Page 468: ...20 16 MCF5272 User s Manual External Bus Interface Types Figure 20 11 Word Write EBI 11 16 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 1 0 BS 3 2 C1 C2 H H H TA ...

Page 469: ... 20 12 Read with Address Setup EBI 11 32 Bit Port Internal Termination Figure 20 13 Longword Write with Address Setup EBI 11 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H H CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H ...

Page 470: ... 20 14 Read with Address Hold EBI 11 32 Bit Port Internal Termination Figure 20 15 Longword Write with Address Hold EBI 11 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H H CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 H H ...

Page 471: ...h Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination Figure 20 17 Longword Write with Address Setup and Address Hold EBI 11 32 Bit Port Internal Termination CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C2 C3 C1 C4 H H H CLKIN A 22 0 D 31 0 OE R W CSn BS 3 0 TA C1 C2 C3 C4 H H ...

Page 472: ...the accessed port size is smaller than 16 bits The MCF5272 hardware supports the following types of burst transfers Sixteen byte cache line read bursts from 32 bit wide SDRAM with access times of n 1 1 1 The value of n depends on read write page miss page hit etc See Chapter 9 SDRAM Controller for complete details of access times To enable this type of transfer CSOR7 EXTBURST must be cleared CSBR7...

Page 473: ...rand is word sized and the transfer requires only two bus cycles Figure 20 18 Example of a Misaligned Longword Transfer Figure 20 19 Example of a Misaligned Word Transfer 20 9 Interrupt Cycles All interrupt vectors are internally generated The MCF5272 does not support external interrupt acknowledge cycles The System Integration Module prioritizes all interrupt requests and issues the appropriate v...

Page 474: ...ception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority Thus the MCF5272 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request 20 10 Bus Errors The system hardware can use the transfer error acknowledge TEA signal to abort the current bus cycle when a fault is dete...

Page 475: ...e strobes and R W Clock 3 C3 During C3 the selected device detects an error and asserts TEA At the end of C3 or Cx the MCF5272 samples the level of TEA If it is asserted the transfer of the longword is aborted and the transfer terminates NOTE This example shows TEA being asserted during C3 TEA can be asserted earlier or later than C3 NOTE If TA is asserted when debug transfer error acknowledge TEA...

Page 476: ...AM controller is not reset This is useful during software debugging since it is preferable to retain SDRAM data in the case of catastrophic system failure In a production system if may be preferable to tie DRESETEN low Master reset resets the entire MCF5272 including the SDRAM controller Master reset occurs when both RSTI and DRESETEN are asserted simultaneously This is the reset that should be ap...

Page 477: ... bus signals CLKIN must be stable by the time VDD reaches the minimum operating specification RSTI and DRESETEN are internally synchronized on consecutive rising and falling clocks before being used They must meet the specified setup and hold times to the falling edge of CLKIN only if recognition by a specific falling edge is required Figure 20 21 Master Reset Timing When the assertion of RSTI is ...

Page 478: ...xternal device asserts RSTI while negating DRESETEN During an external normal reset RSTI must be asserted for a minimum of six CLKINs Figure 20 22 is a functional timing diagram of external normal reset operation illustrating relationships among RSTI DRESETEN RSTO mode selects and bus signals RSTI and DRESETEN are internally synchronized on consecutive falling and rising clocks before being used a...

Page 479: ...sertion of RSTI with DRESETEN negated caused the previous reset 20 12 3 Software Watchdog Timer Reset Operation A software watchdog timer is provided to allow periodic monitoring of software activity If the software watchdog is not periodically accessed by software it can programmed to generate a reset after a timeout period When the timeout occurs an internal reset is asserted for 32K clocks rese...

Page 480: ...he time of the software watchdog reset you must assert RSTI during software watchdog reset to cause the mode pins to be resampled 20 12 4 Soft Reset Operation If the soft reset bit SCR SOFTRST is programmed to generate a reset RSTO is asserted for 128 clocks resetting all external devices as with a normal or master reset All internal peripherals with the exception of the SIM chip select interrupt ...

Page 481: ... reset the SDRAM controller unless DRESETEN is asserted during the reset When DRESETEN is negated SDRAM refreshes continue to be generated during and after reset at the programmed rate and with the programmed waveform timing During the soft reset period all bus signals continue to operate normally ...

Page 482: ...20 30 MCF5272 User s Manual Reset Operation ...

Page 483: ... register and three test registers a 1 bit bypass register a 265 bit boundary scan register and a 32 bit ID register The boundary scan register links the device s pins into one shift register The contents of this register can be found at the ColdFire website at http www motorola com semiconductors Test logic implemented using static logic design is independent of the device system logic The TAP in...

Page 484: ...ve output pins to stable levels NOTE Precautions to ensure that the IEEE 1149 1 test logic does not interfere with non test operation are described in Section 21 7 Non IEEE 1149 1 Operation Figure 21 1 shows the MCF5272 implementation of IEEE 1149 1 Figure 21 1 Test Access Port Block Diagram 21 2 JTAG Test Access Port and BDM Debug Port The JTAG test interface shares pins with the debug modules Th...

Page 485: ...ed by the IEEE 1149 1 standard Connecting TMS to VDD disables the test controller making all JTAG circuits transparent to the system TDO DSO Test and debug data out Output for shifting data out of serial data port logic Shifting out data depends on the state of the JTAG controller state machine and the instructions in the instruction register The shift occurs on the falling edge of TCK When not ou...

Page 486: ... that when bidirectional data bits are sampled bit data can be interpreted only after examining the I O control bit to determine pin direction Open drain bidirectional bits require separate input and output cells as no direction control is available from which to determine signal direction Programmable open drain signals also have an enable cell XXX de to select whether the pin is open drain or pu...

Page 487: ... 21 3 Output Cell O Cell BC 1 Figure 21 4 Input Cell I Cell Observe only BC 4 MUX Update DR G1 1 EXTEST CLAMP HI Z 0 Otherwise To output buffer To next cell Shift DR From last cell Clock DR Data from system logic 1 1 MUX G1 1 1 1 D C1 1 D C1 1 MUX 1 G1 FROM LAST CELL 1 D C1 CLOCK DR SHIFT DR TO NEXT CELL FROM INPUT BUFFER TO SYSTEM LOGIC ...

Page 488: ...irection To next cell Shift DR From last cell Clock DR Output control from system logic 1 1 MUX G1 1 1 1 D C1 1 D C1 0 HI Z 1 Otherwise To output buffer MUX Update DR G1 1 EXTEST CLAMP HI Z 0 Otherwise To next cell Shift DR From last cell Clock DR Data from system logic 1 1 MUX G1 1 1 1 D C1 1 D C1 To output buffer From input buffer 1 Output MUX G1 1 1 MUX G1 1 1 0 Input Data to system logic ...

Page 489: ... 0 Instruction Description 0000 EXTEST The external test EXTEST instruction selects the boundary scan register EXTEST asserts internal reset for the MCF5272 system logic to force a predictable benign internal state while performing external boundary scan operations By using the TAP the register is capable of a scanning user defined values into the output buffers b capturing values presented to inp...

Page 490: ... backdrive the output pins and protect the input pins from random toggling during circuit board testing The HIGHZ instruction selects the bypass register forcing all output and bidirectional pins to the high impedance state The HI Z instruction goes active on the falling edge of TCK in the update IR state when the data held in the instruction shift register is equivalent to octal 5 1100 CLAMP When...

Page 491: ... to system logic by forcing the TAP controller into test logic reset state which takes at least five consecutive TCK rising edges with TMS high TMS has an internal pull up resistor and may be left unconnected If TMS is unconnected or connected to VCC the TAP controller cannot exit test logic reset state regardless of the TCK state This requires the TMS TCK and TDI inputs to be high ...

Page 492: ...21 10 MCF5272 User s Manual Non IEEE 1149 1 Operation ...

Page 493: ... USB_D PB5 TA RSTO VDD VDD GND GND VDD VDD D12 PC12 D24 D8 D25 D9 D26 D10 G USB_VDD USB_GND PB4 URT0_CLK PB6 VDD GND GND GND GND VDD D11 PC11 D27 D11 D28 D12 D29 D13 H PB1 URT0_RXD PB2 URT0_CTS PB3 URT0_RTS PB0 URT0_TXD VDD GND GND GND GND VDD D10 PC10 SDBA1 D31 D15 D30 D14 J USB_CLK PA8 FSC0 FSR0 PA9 DGNT0 DCL0 URT1_CLK VDD VDD GND GND VDD VDD D7 D8 D9 SDBA0 K DIN0 URT1_RXD URT1_CTS URT1_RTS INT5...

Page 494: ...or pin 1 identification in this area 14 13 12 11 5 4 3 2 B C D E F G H J K L 4 NOTES 1 Dimensions are in millimeters 2 Interpretdimensionsandtolerances per ASME Y14 5M 1994 3 Dimension B is measured at the maximum solder ball diameter parallel to datum plane Z 4 Datum Z seating plane is defined by the spherical crowns of the solder balls 5 Parallelism measurement shall exclude any effect of mark o...

Page 495: ...define maximum conditions to which the MCF5272 may be subjected without being damaged However the device cannot operate normally while exposed to these electrical extremes This device contains circuitry that protects against damage from high static voltages or electrical fields however normal precautions should be taken to avoid application of voltages higher than maximum rated voltages to this hi...

Page 496: ...design to prevent device junction temperatures from exceeding the rated specification System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices Conformance to the device junction temperature specification can be verified by physical measurement in the customer s system using the Ψjt parameter the device power dissipat...

Page 497: ...al high input current VIH 2 0 V TMS BKPT TDI DSI TRST DSCLK IIH 0 1 mA Output high voltage VOH 2 4 V Output low voltage VOL 0 5 V Pin capacitance1 Cin 10 pF 1 This specification periodically sampled but not 100 tested Table 23 5 I O Driver Capability Signal Drive Capability Output Load CL A 22 0 7 mA 30 pF D 31 0 7 mA 30 pF CS 6 0 4 mA 30 pF BS 7 mA 30 pF OE RD 4 mA 30 pF DACK HIZ 4 mA 30 pF TC BY...

Page 498: ...PA 13 0 2 mA 30 pF PA14 4 mA 30 pF PA15_INT6 2 mA 30 pF PB0 PB3 PB7 4 mA 30 pF PB 2 1 PB 6 4 2 mA 30 pF PB 10 8 4 mA 30 pF PB 15 11 2 mA 30 pF USB_D 1 8 mA USB_D 1 8 mA DOUT1 2 mA 30 pF FSC1 2 mA 30 pF DCL1 4 mA 30 pF URT2_CTS 2 mA 30 pF URT2_RTS 2 mA 30 pF URT2_TxD 2 mA 30 pF QSPI_Dout 4 mA 30 pF QSPI_CLK 4 mA 30 pF QSPI_CS0 2 mA 30 pF PWM_OUT 3 1 4 mA 30 pF E_TxD0 5 mA 30 pF E_TxEN 2 mA 30 pF E_...

Page 499: ... rising edge of a reference clock The reference clock is the SDCLK output All other timing relationships can be derived from these values Table 23 6 Clock Input and Output Timing Specifications Name Characteristic 0 66 MHz Unit Min Max Frequency of operation 0 66 00 MHz C1 CLKIN period T 1 1 The clock period is referred to as T in the electrical specifications The time for T is always in nS Timing...

Page 500: ...met only if recognition is needed on a particular clock edge RSTI valid to SDCLK setup 6 nS B1b 2 TA valid to SDCLK setup 6 nS B1c 2 TEA valid to SDCLK setup 5 nS B1d 2 INTx valid to SDCLK setup 6 nS B1e 2 BKPT valid to PSTCLK setup 9 nS B1f Mode selects BUSW 1 0 WSEL HIZ valid to PSTCLK setup when RSTI asserted 6 nS B2d SDCLK to asynchronous control inputs RSTI TA TEA INTx BKPT invalid hold 0 nS ...

Page 501: ...g Requirements 23 3 3 Processor Bus Output Timing Specifications Table 23 8 lists processor bus output timings Invalid Invalid SDCLK Output TSETUP THOLD Input Setup And Hold 1 5V trise 1 5 nS Vh VIH Vl VIL 1 5V 1 5V Valid tfall 1 5 nS Vh VIH Vl VIL Input Rise Time Input Fall Time The timings are also valid for inputs sampled on the negative clock edge Inputs SDCLK B4 B5 ...

Page 502: ...cifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max Control Outputs B6a SDCLK to chip selects CS 6 0 valid 11 nS B6b SDCLK to byte enables BS 3 0 valid 8 5 nS B6c SDCLK to output enable OE valid 8 5 nS B6d SDCLK to write enable R W valid 8 nS B6e SDCLK to reset output RSTO valid 7 4 nS B...

Page 503: ... E L I M I N A R Y Figure 23 3 Read Write SRAM Bus Timing Figure 23 4 shows an SRAM bus cycle terminated by TA showing timings listed in Table 23 8 SDCLK CSn A 22 0 OE R W BS 3 0 D 31 0 TA H H S0 S2 S4 S5 S1 S3 S0 S1 S2 S3 S4 S5 S0 S1 S2 TEA H B6a B8 B7a B9 B6c B7a B6b B7b B4 B5 B11 B12 B6d B7b B7a B6a B9 B8 B6b B7b B13 ...

Page 504: ...ifications P R E L I M I N A R Y Figure 23 4 SRAM Bus Cycle Terminated by TA Figure 23 5 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 23 8 SDCLK CSn A 22 0 OE R W BS 3 0 TA H S0 S2 S4 S5 S1 S3 SW0 SW1 S0 S1 TEA H B6a B8 B7a B9 B6c B7a B6b B7b B2d B1b D 31 0 B4 B5 ...

Page 505: ...shows reset and mode Select HIZ configuration timing showing parameters listed in Table 23 8 Figure 23 6 Reset and Mode Select HIZ Configuration Timing SDCLK CSn A 22 0 OE R W BS 3 0 D 31 0 TA H S0 S2 S4 S5 S1 S3 SW0 SW1 S0 S1 TEA H B6a B8 B7a B9 B6c B7a B6b B7b B2d B1c RSTI Mode selects SDCLK BUSW 1 0 WSEL HIZ B3 B1f B2e Reset is asynchronous Assert for at least 2 consecutive SDCLK rising edges ...

Page 506: ...s BDM serial port AC timing for the values in Table 23 9 Figure 23 8 BDM Serial Port AC Timing Table 23 9 Debug AC Timing Specification Num Characteristic 0 66 MHz Units Min Max D1 PST 3 0 DDATA 3 0 to PSTCLK valid 8 5 nS D2 PSTCLK to PST 3 0 DDATA 3 0 hold 1 nS D3 DSI to DSCLK setup 1 PSTCLKs D4 1 1 DSCLK and DSI are synchronized internally D4 is measured from the synchronized DSCLK input relativ...

Page 507: ...1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max Control Inputs SD1 SDCLK to address output A 22 0 valid 8 5 nS SD2 SDCLK to address output A 22 0 invalid output hold 1 SD3 SDCLK to DQM 3 0 valid 9 nS SD4 SDCLK to DQM 3 0 invalid output hold 2 SD5 SDCLK to data output D 31 0 valid signal from driven or three state 8 n...

Page 508: ... I N A R Y Figure 23 9 SDRAM Signal Timing SDCLK DATA IN READ SDCR DATA OUT WRITE SD1 RAS0 CAS0 SDADR 13 0 DQMx SD3 SD5 SD6 SD16 SD14 SD8 SD7 SD7 SD8 SDWE SD8 SD7 SDBA 1 0 SD7 SD4 DATA IN SD16 SD15 READ SDCR b4 0 b4 1 A10_PRECHG SD12 SD11 T0 T1 T2 T3 T4 T5 T6 Col Col Col Col SDCS SD10 SD9 SD2 SD8 SDCLKE SD8 SD7 SD13 ...

Page 509: ...ions correctly up to a E_RxCLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed twice the E_RxCLK frequency Table 23 11 lists MII receive channel timings Figure 23 11 shows MII receive signal timings listed in Table 23 11 Table 23 11 MII Receive Signal Timing Num Characteristic 1 1 E_RxDV E_RxCLK and E_RxD0 have same timi...

Page 510: ...xER can be programmed to transition from either the rising or falling edge of E_TxCLK and the timing is the same in either case This options allows the use of non compliant MII PHYs Refer to the Ethernet chapter for details of this option and how to enable it Figure 23 12 shows MII transmit signal timings listed in Table 23 12 Table 23 12 MII Transmit Signal Timing Num Characteristic1 1 E_TxCLK ET...

Page 511: ...maximum MDC frequency of 2 5 MHz Figure 23 14 shows MII serial management channel timings listed in Table 23 14 Table 23 13 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M91 1 E_COL has the same timing in 10 Mbit 7 wire interface mode E_CRS E_COL minimum pulse width 1 5 E_TxCLK period Table 23 14 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MDC falling ...

Page 512: ...le AC timings Figure 23 15 shows timer module timings listed in Table 23 15 Table 23 15 Timer Module AC Timing Specifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max T1 TIN1 cycle time 3T nS T2 TIN1 valid to SDCLK setup 6 nS T3 SDCLK to TIN 1 0 invalid hold 0 nS T4 TIN1 pulse width 1T nS...

Page 513: ...ons Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max UT1 URTnRxD valid to SDCLK setup 6 nS UT2 SDCLK to URTn_RxD invalid hold 0 nS UT3 URTn_CTS valid to SDCLK setup 6 nS UT4 SDCLK to URTn_CTS invalid hold 0 nS UT5 SDCLK to URTn_TxD valid 7 nS UT6 SDCLK to URTn_TxD invalid output hold 3 nS UT7 SDC...

Page 514: ...72 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Debug AC Timing Specifications P R E L I M I N A R Y Figure 23 16 UART Timing UT5 SDCLK URTn_TxD UT6 UT1 UT2 URTn_RxD UT7 URTn_RTS UT8 UT3 UT4 URTn_CTS ...

Page 515: ...f GDCL1_OUT to rising edge of DFSC 3 1 20 nS P3 Delay from rising edge of GDCL1_OUT to DFSC 3 1 Invalid output Hold 2 nS P4 3 2 3 GDCL1_OUT must be less than 1 20th of the CPU operating frequency This is to ensure minimum jitter to CODECs that may be connected to Ports 1 2 3 GDCL1_OUT clock period 20T P5 4 2 4 Based on generated GDCL1_OUT less than 1 20 of CPU clock frequency GDCL1_OUT pulse width...

Page 516: ...6a DCL0 to FSR0 or FSC0 input Invalid hold time 25 nS P16b DCL1 to FSR1 or FSC1 input Invalid hold time 25 nS P17a Delay from rising edge of DCL0 to low z and valid data on DOUT0 30 nS P17b Delay from rising edge of DCL1 to low z and valid data on DOUT1 and DOUT3 30 nS P19a Delay from rising edge of DCL0 to high z on DOUT0 30 nS P19b Delay from rising edge of DCL1 to high z on DOUT1 and DOUT3 30 n...

Page 517: ...after the falling edge of DCL1 hold time 25 nS P33 DCL0 DCL1 clock frequency 8192 KHz P34 DCL0 DCL1 pulse width low 45 55 of DCL period P35 DCL0 DCL1 pulse width high 45 55 of DCL period P38 Delay from rising edge of FSC0 to low z and valid data on DOUT0 Delay from rising edge of FSC1 to low z and valid data on DOUT1 Delay from rising edge of DFSC2 to low z and valid data on DOUT1 Delay from risin...

Page 518: ...Data valid on DIN1 or DIN3 after rising edge of DCL1 25 nS Table 23 20 GCI Master Mode Timing PLIC PORTs 1 2 3 Name Characteristic Min Max Unit Name P50 1 Delay from rising edge of GDCL1_OUT to rising edge of DFSC 1 3 20 nS P51 1 Delay from rising edge of GDCL1_OUT to falling edge of DFSC 1 3 20 nS P52 2 3 GDCL1_OUT clock period 20T nS P53 2 4 GDCL1_OUT pulse width low 45 50 55 of period P54 2 4 G...

Page 519: ...nS P60 Data valid on DIN 1 2 before rising edge of GDCL1_OUT setup time 25 nS P61 Data valid on DIN 1 2 after rising edge of GDCL1_OUT hold time 25 nS 1 For most telecommunications applications the period of DFSC 1 3 should be set to 125 µS Refer to clock generator planning in PLIC chapter 2 GDCL1_OUT must be less than 1 20th of the CPU operating frequency to ensure minimum jitter to CODECs connec...

Page 520: ...to PORTx output valid 9 nS P4 SDCLK to PORTx output invalid output hold 3 nS Table 23 22 USB Interface AC Timing Specifications Name Characteristic 48 66 MHz Unit Min Max US1 USB_CLK frequency of operation 1 1 USB_CLK accuracy should be 500ppm or better USB_CLK may be stopped to conserve power 48 48 MHz US2 2 2 Specification values are not tested USB_CLK fall time from Vh 2 4V to Vl 0 5V 2 nS US3 ...

Page 521: ...n 0 10 MHz J1 TCK cycle time 100 nS J2a TCK clock pulse high width measured at 1 5 V 40 nS J2b TCK clock pulse low width measured at 1 5 V 40 nS J3a TCK fall time from Vh 2 4 V to Vl 0 5 V 5 nS J3b TCK rise time from Vl 0 5 V to Vh 2 4 V 5 nS J4 TDI TMS to TCK rising setup 10 nS J5 TCK rising edge to TDI TMS invalid hold 15 nS J6 Boundary scan data valid to TCK rising edge setup 10 nS J7 Boundary ...

Page 522: ...Name Characteristic 1 0 66 MHz Unit Min Max QS1 2 SDLCK high to QSPI chip selects valid 25 nS QS2 2 SDLCK high to QSPI chip selects invalid Output hold 2 nS QS32 SDLCK high to QSPI_CLK valid 12 5 nS QS42 SDLCK high to QSPI_CLK invalid Output hold 2 nS QS5 3 QSPI_CLK high to QSPI_DOUT valid 18 nS QS6 3 QSPI_CLK high to QSPI_DOUT invalid Output hold 2 nS QS7 SDCLK high to QSPI_DOUT valid 30 nS QS82 ...

Page 523: ...to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 2 Parameter tested 3 Parameter by design Table 23 25 PWM Modules AC Timing Specifications Name Characteristic 1 1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0 0 66 MHz Unit Min Max PW1 2 2 Parameter tested SDLCK high to PWM_OUT 2 0 valid high or low 11 nS...

Page 524: ... User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Debug AC Timing Specifications P R E L I M I N A R Y The values in Table 23 25 correspond to Figure 23 25 Figure 23 25 PWM Timing PWM_OUT 2 0 SDCLK PW1 PW2 ...

Page 525: ...absolute address of a given register Absolute address MBAR register offset A 2 List of Memory Map Tables Table A 1 On Chip Module Base Address Offsets from MBAR Module Module Base Address Mnemonic Configuration Registers MBAR 0x0000 CFG_Base Interrupt Registers MBAR 0x0020 INT_Base Chip Select Registers MBAR 0x0040 CS_Base Ports Registers MBAR 0x0080 GPIO_Base QSPI Module Registers MBAR 0x00A0 QSP...

Page 526: ...ta registers D7 D0 MOVE RDREG WDREG 0x0801 VBR 32 Vector Base Register MOVEC RCREG WCREG 0x080E CCR 8 Condition Code Register Debug only MOVE to from CCR RCREG WCREG 0x080F PC 32 Program Counter Debug only RCREG WCREG 0x0C00 ROMBAR 32 ROM Base Address Register MOVEC RCREG WCREG 0x0C04 RAMBAR 32 SRAM Base Address Register MOVEC RCREG WCREG 0x0C0F MBAR 32 Module Base Address Register MOVEC Table A 3...

Page 527: ...AR Offset 31 24 23 16 15 8 7 0 0x0040 CS Base Register 0 CSBR0 0x0044 CS Option Register 0 CSOR0 0x0048 CS Base Register 1 CSBR1 0x004C CS Option Register 1 CSOR1 0x0050 CS Base Register 2 CSBR2 0x0054 CS Option Register 2 CSOR2 0x0058 CS Base Register 3 CSBR3 0x005C CS Option Register 3 CSOR3 0x0060 CS Base Register 4 CSBR4 0x0064 CS Option Register 4 CSOR4 0x0068 CS Base Register 5 CSBR5 0x006C ...

Page 528: ...er QWR Reserved 0x00AC QSPI Interrupt Register QIR Reserved 0x00B0 QSPI Address Register QAR Reserved 0x00B4 QSPI Data Register QDR Reserved Table A 8 PWM Module Memory Map MBAR Offset 31 24 23 16 15 8 7 0 0x00C0 PWM Control Register 1 PWCR1 Reserved 0x00C4 PWM Control Register 2 PWCR2 Reserved 0x00C8 PWM Control Register 3 PWCR3 Reserved 0x00D0 PWM Pulse Width Register 1 PWWD1 Reserved 0x00D4 PWM...

Page 529: ...T0 Transmit Buffer U0TxB Reserved 0x0110 UART0 CTS Change Register U0CCR Reserved 0x0110 UART0 Auxiliary Control Register U0ACR Reserved 0x0114 UART0 Interrupt Status Register U0ISR Reserved 0x0114 UART0 Interrupt Mask Register U0IMR Reserved 0x0118 UART0 Baud Prescaler MSB U0BG1 Reserved 0x011C UART0 Baud Prescaler LSB U0BG2 Reserved 0x0120 UART0 AutoBaud MSB Register U0ABR1 Reserved 0x0124 UART0...

Page 530: ...Reserved 0x014C UART1 Transmit Buffer U1TxB Reserved 0x0150 UART1 CTS Change Register U1CCR Reserved 0x0150 UART1 Auxiliary Control Register U1ACR Reserved 0x0154 UART1 Interrupt Status Register U1ISR Reserved 0x0154 UART1 Interrupt Mask Register U1IMR Reserved 0x0158 UART1 Baud Prescaler MSB U1BG1 Reserved 0x015C UART1 Baud Prescaler LSB U1BG2 Reserved 0x0160 UART1 AutoBaud MSB Register U1ABR1 Re...

Page 531: ...x020C Timer 0 Counter Register TCN0 Reserved 0x0210 Timer 0 Event Register TER0 Reserved 0x0220 Timer 1 Mode Register TMR1 Reserved 0x0224 Timer 1 Reference Register TRR1 Reserved 0x0228 Timer 1 Capture Register TCAP1 Reserved 0x022C Timer 1 Counter Register TCN1 Reserved 0x0230 Timer 1 Event Register TER1 Reserved 0x0240 Timer 2 Mode Register TMR2 Reserved 0x0244 Timer 2 Reference Register TRR2 R...

Page 532: ...eive P3DRR 0x0328 Port0 B1 Data Transmit P0B1TR 0x032C Port1 B1 Data Transmit P1B1TR 0x0330 Port2 B1 Data Transmit P2B1TR 0x0334 Port3 B1 Data Transmit P3B1TR 0x0338 Port0 B2 Data Transmit P0B2TR 0x033C Port1 B2 Data Transmit P1B2TR 0x0340 Port2 B2 Data Transmit P2B2TR 0x0344 Port3 B2 Data Transmit P3B2TR 0x0348 Port0 D Data Transmit P0DTR 0x0349 Port1 D Data Transmit P1DTR 0x034A Port2 D Data Tra...

Page 533: ...SR Reserved Loop back Control PLCR 0x0392 Reserved D Channel Request PDRQR 0x0394 Port0 Sync Delay P0SDR Port1 Sync Delay P1SDR 0x0398 Port2 Sync Delay P2SDR Port3 Sync Delay P3SDR 0x039C Reserved Clock Select PCSR Table A 15 Ethernet Module Memory Map MBAR Offset 31 24 23 16 15 8 7 0 0x0840 Ethernet Control Register ECR 0x0844 Ethernet Interrupt Event Register EIR 0x0848 Ethernet Interrupt Mask R...

Page 534: ...R 0x1010 Reserved USB Function Address Register FAR 0x1014 USB Alternate Setting Register ASR 0x1018 USB Device Request Data1 Register DRR1 0x101C USB Device Request Data2 Register DRR2 0x1020 Reserved USB Specification Number Register SPECR 0x1024 Reserved USB Endpoint 0 Status Register EP0SR 0x1028 USB Endpoint 0 IN Config Register IEP0CFG 0x102C USB Endpoint 0 OUT Config Register OEP0CFG 0x1030...

Page 535: ...ter EP7ISR 0x108C USB Endpoint 0 Interrupt Mask Register EP0IMR 0x1090 Reserved USB Endpoint 1 Interrupt Mask Register EP1IMR 0x1094 Reserved USB Endpoint 2 Interrupt Mask Register EP2IMR 0x1098 Reserved USB Endpoint 3 Interrupt Mask Register EP3IMR 0x109C Reserved USB Endpoint 4 Interrupt Mask Register EP4IMR 0x10A0 Reserved USB Endpoint 5 Interrupt Mask Register EP5IMR 0x10A4 Reserved USB Endpoi...

Page 536: ...EP4DPR 0x10E0 Reserved USB Endpoint 5 Data Present Register EP5DPR 0x10E4 Reserved USB Endpoint 6 Data Present Register EP6DPR 0x10E8 Reserved USB Endpoint 7 Data Present Register EP7DPR 0x1400 0x17FF USB Configuration RAM 1 K Bytes Table A 16 USB Module Memory Map Continued MBAR Offset 31 24 23 16 15 8 7 0 ...

Page 537: ...eds Minimize capacitive loading on signals to SDRAMs Operation of MCF5272 at highest frequencies i e 66MHz requires clean signals to ensure setup and hold times are met and to minimize EMC noise in terms of overshoot and undershoot of signals What to do Add buffers on address and control signals shared by SDRAM and other peripherals NEVER put buffers between the MCF5272 device and the SDRAMs Put t...

Page 538: ...RA6 RA7 RA8 RA9 RA10 RA3 SDRAM Flash D31 D0 Device D31 D0 1 Device D31 D0 2 Device D31 D0 3 CS0 CS1 CS2 CS3 32 OE CS0 CS1 CS2 CS3 D31 D0 Signals M CF5272 CS7 32 n DIR EN B 7 0 A 7 0 74LVC245 Signal BS 3 0 Ax A2 32 bit bus Ax A1 16 bit bus RA1 RA2 RA3 R1 R2 Resistor Arrays 10 75 ohms resistor 10 75 ohms ...

Page 539: ... operation 20 28 software watchdog timer reset operation 20 27 transfer acknowledge TA 20 3 transfer error acknowledge TEA 20 4 Byte strobes 20 10 C Cache configuration register 2 19 registers access control 2 20 Cache control register 4 13 Caches coherency and validation 4 9 miss fetch algorithm line fills 4 11 CAM interface 11 6 CCR 2 17 Chip select base registers 8 3 CS0 special case 8 2 option...

Page 540: ...escriptor active register 11 15 descriptor ring register pointer to receive 11 28 pointer to transmit 11 29 error handling 11 10 FEC initialization 11 32 FIFO receive bound register 11 20 receive start register 11 20 transmit start register 11 22 frame reception 11 5 transmission 11 4 hardware initialization 11 31 hash table algorithm 11 8 high register 11 27 low register 11 28 initialization sequ...

Page 541: ... 20 21 PLIC GCI 13 11 request inputs 19 21 J JTAG BDM debug port 21 2 boundary scan register 21 4 IDCODE register 6 11 instruction register 21 7 overview 21 1 restrictions 21 8 TAP controller 21 3 test access port 21 2 L Local memory module interactions 4 1 registers 4 2 Loopback Ethernet internal and external 11 9 M MAC data representation 3 5 hardware support 2 13 instruction execution timings 3...

Page 542: ...ata 13 7 unencoded data 13 8 D Channel request register 13 33 D Channel status register 13 32 frame sync synthesis 13 14 GCI C I channel receive registers 13 29 transmit registers 13 31 transmit status register 13 31 GCI interrupts aperiodic status 13 11 GCI monitor channel receive registers 13 26 transmit abort register 13 28 transmit registers 13 27 transmit status register 13 28 GCI IDL B and D...

Page 543: ...R 5 6 5 9 access control 2 20 4 15 activate low power 6 10 address 2 16 address A0 A6 2 16 ALPR 6 10 B2 data transmit 13 19 BI data receive 13 16 cache configuration 2 19 cache control 4 13 CACR 2 19 CCR 2 17 chip select base 8 3 general 8 2 option 8 5 condition code 2 17 2 17 condition code CCR 2 17 CSBR 8 3 CSOR 8 5 CSR 5 9 D data receive 13 17 D0 D7 2 16 data 2 16 data breakpoint mask 5 11 data...

Page 544: ... select 13 34 D data transmit 13 19 D Channel status 13 32 GCI C I channel receive 13 29 transmit 13 31 GCI monitor channel general 13 26 transmit 13 27 transmit status 13 28 general 13 16 interrupt configuration 13 22 loopback control 13 21 memory map 13 15 periodic status 13 24 port configuration 13 20 receive data 13 4 sync delay 13 34 transmit data 13 5 PMR 6 7 pointer to receive descriptor ri...

Page 545: ...verview 4 6 power management programming 4 7 S SDCR 9 13 SDRAM auto initialization 9 10 banks page hits page misses 9 6 configuration register 9 7 controller signals 9 1 devices interface 9 5 interface 9 16 performance 9 11 power down and self refresh 9 10 read accesses 9 17 refresh timing 9 21 registers 9 7 solving timing issues 9 13 timing register 9 9 write accesses 9 19 Serial management chann...

Page 546: ...ands 2 33 USART AC 23 19 USB interface AC 23 26 Timings SDRAM refresh 9 21 Transmit signal timing 23 16 U UART modules bus operation interrupt acknowledge cycles 16 31 read cycles 16 31 write cycles 16 31 clock source baud rates 16 21 external clock 16 22 FIFO stack in UART0 16 26 initialization sequence 16 32 looping modes 16 28 automatic echo 16 28 local loop back 16 28 remote loop back 16 29 mo...

Page 547: ... recommendations 12 36 register access 12 29 descriptions 12 9 12 27 remote wakeup and resume operation 12 34 request processor 12 5 software architecture and application notes 12 30 transceiver interface 12 4 User programming model 2 16 V Variant address 5 5 Vector base register 2 19 2 19 Version 2 ColdFire core overview 1 4 W Wait state generation overview 1 5 Watchdog counter register 6 14 even...

Page 548: ...INDEX Index 12 MCF5272 User s Manual ...

Page 549: ...s USB Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus Operation Appendix B Buffering and Impedence Matching Index Appendix A List of Memory Maps 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 A 6 20 B IND 21 23 22 IEEE 1149 1 Test Access Port JTAG Me...

Page 550: ...SB Physical Layer Interface Controller PLIC Queued Serial Peripheral Interface QSPI Module Timer Module UART Modules General Purpose I O Module Pulse Width Modulation PWM Module Signal Descriptions Bus Operation Appendix B Buffering and Impedence Matching Index Appendix A List of Memory Maps 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 A 6 20 B IND 21 23 22 IEEE 1149 1 Test Access Port JTAG Mecha...

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