Motorola ASTRO MT 1500, Service Manual, Page: 124 / 817

August 16, 2007 6816985H01-B
4.4-4 700/800 MHz Detailed Theories of Operation: Transmitter
4.4.4.2 Back End
In the ABACUS IC (U401) , the first IF frequency is amplified and then down-converted to the second
IF frequency (2.25 MHz). At this point, the analog signal is converted into two digital bit streams by a
sigma-delta A/D converter. The bit streams are then digitally filtered, mixed down to baseband, and
filtered again. The output data stream is then sent to the Patriot IC, where it is decoded to produce
the recovered audio.
The ABACUS IC (U401) is electronically programmable. The amount of filtering, which is dependent
on the radio channel spacing and signal type, is controlled by the microcomputer. Additional filtering,
which used to be provided externally by a conventional ceramic filter, is replaced by internal digital
filters in the ABACUS IC.
The ABACUS IC contains a feedback Automatic Gain Control (AGC) circuit to expand the dynamic
range of the sigma-delta converter. The differential output data contains the quadrature (I and Q)
information in 16-bit words, the AGC information in a 9-bit word, imbedded word sync information,
and fill bits. Two synthesizers are available on the chip for second LO and sampling clock (18 MHz)
generation.
The second LO/VCO is a Colpitts oscillator built around transistor Q401. A varactor diode (D401) in
the VCO is used to adjust the VCO frequency. The control signal for the varactor is derived from a
loop filter consisting of C409, R405, C416, R403, and C415. The sampling clock is derived from a
negative resistance generator (on the chip) available at CLKP, CLKN, and a external tank circuit
(L405, C443, and D402). The loop filter for the clock is realized by C444, R411, and C450.
4.4.5 Transmitter
The 7/800MHz RF power amplifier (PA) consists of:
1. RF driver ( U101 )
2. Silicon N-Channel MOSFET Power Amplifier ( Q101 )
For 7/800MHz band, an RF input drive level of approxi3dBm is supplied from the VCO buffer
IC (
U250 ). This input drive level is applied to pin 16 (RFIN) of U101 . The DC power is applied to pins
6, 7, and 14 of U101 and to the drain of Q101 via a filtered RAW_B+. Power control is achieved
through the varying of the dc bias (and thus the gain) to pin 1 of U101 and the gate of Q101 . The
amplified RF signal leaves the RF final PA ( Q101 ) at the drain and is applied to the directional
coupler ( U106 ) via an impedance match. The RF signal passes through the coupler, a discrete
antenna switch, and a discrete harmonic filter before finally reaching the antenna launch connector.
A portion of the forward RF power is sampled by the directional coupler ( U106 ), applied to the diode
( D103 ) for rectification, and the resulting DC signal is fed back to pin 1 of the Power Control IC
( PCIC, U102 ). This DC signal is representative of the forward RF power being passed through the
directional coupler U106 ). The DC signal is used by the PCIC to regulate the transmitted RF power
level.
The PCIC is the heart of the power control loop. The rectified feedback is internally compared to an
internal Digital-to-Analog Converter (DAC) output voltage in the PCIC to determine the amount of DC
bias voltage at pin 4. This voltage at pin 4 of the PCIC controls the gain (and thus the output power,
as explained above) of the RF driver (
U101 ) and the N-Channel MOSFET final ( Q101 ) via a fixed
resistor divider network.