miniDSP Ltd, Hong Kong /
/ Features and specifications subject to change without prior notice
9
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If driving longer lines, buffers may be required for the clock signals (MCLK, LRCLK, and BLCK).
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Observe correct grounding and shielding, and keep analog and digital grounds separated.
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Ensure that the clock ratios (as listed in Table 2) are compatible with connected circuits.
3.3V logic level
All lines use a 3.3V logic level. Ensure that connected circuits use a compatible level (1.8V, for example, will
not work).
2.6
DSP
SETTINGS PARAMETERS
The below settings are the default parameters of the internal DSP library. We hope in the near future to provide
an easy to use GUI to control these parameters. Stay tuned.
