System Core, Boot Configuration and On-Board Memory 5
miriac SBC-LX2160A User Manual
V 1.6
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© MicroSys Electronics GmbH 2021
5
System Core, Boot Configuration
and On-Board Memory
5.1
Processor NXP LX2160A
The LX2160A
Processor by NXP is a QorIQ Layerscape CPU with 16 Cortex-A72
cores. It exposes a wide variety of external interfaces, which are explained in detail
in the following chapters. Variations with 12 and 8 cores are available.
The cores run at a maximum clock speed of 2200MHz, 2000MHz or 1800MHz
respectively, depending on the ordered type. The CPU frequency can be clocked
down if necessary.
5.2
JTAG Chain
The JTAG 1 chain of the SBC-LX2160A includes the LX2160A processor ONLY.
JTAG 1 is available on connector
“
ST41
”
.
The JTAG 2 chain of the SBC-LX2160A includes the 40/100G and both 10G
Ethernet PHYs. The JTAG 2 port is available via
connector “ST55”.
For interfacing standard debugger pinouts an additional intermediate adapter may
be necessary, Please see chapter 6.12 for the pinout of the JTAG connectors.
5.3
Reset Structure
Pin
Number
on ST1
Signal Name
Signal
Direction
Function
A10
RESIN#
Input to the
module
Active low module reset:
while active the module is held in reset state
1,8V level
A9
RESET_OUT#
Output from
the module
Active low peripheral reset:
while active peripheral devices shall be held in
reset state
1,8V level
Table 5-1 Reset signal overview
RESIN# (to module) is generated from the power rail monitoring by two quintuple
voltage supervisors with push-button reset. RESIN# may also be forced by SW2.
All devices on the carrier are reset if RESIN# or RESET_OUT# (from module) ist
active.
