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UG0651

User Guide

Scaler

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Summary of Contents for UG0651

Page 1: ...UG0651 User Guide Scaler ...

Page 2: ...e suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or ...

Page 3: ... 1 Revision 4 0 vi 1 2 Revision 3 0 vi 1 3 Revision 2 0 vi 1 4 Revision 1 0 vi 2 Introduction 1 3 Hardware Implementation 3 3 1 Inputs and Outputs 4 3 2 Configuration Parameters 5 3 3 FSM Implementation 6 3 4 Timing Diagram 7 3 5 Testbench 7 3 6 Resource Utilization 12 ...

Page 4: ...sign Testbench Dialog Box 8 Figure 7 Scaler 9 Figure 8 Scaler Core on SmartDesign Testbench Canvas 9 Figure 9 Promote to Top Level Option 9 Figure 10 Scaler Ports Promoted to Top Level 10 Figure 11 Generate Component 10 Figure 12 Import Files Option 10 Figure 13 Input File Selection 11 Figure 14 Input File in Simulation Directory 11 Figure 15 Simulating Pre Synthesis Design 11 Figure 16 ModelSim T...

Page 5: ...UG0651 User Guide Revision 4 0 v Tables Table 1 Scaler Input and Output Ports 4 Table 2 Configuration Parameters 5 Table 3 Testbench Configuration Parameters 7 Table 4 Resource Utilization Report 12 ...

Page 6: ...figuration parameters were updated For more information see Table 2 page 5 Timing diagram was updated For more information see Figure 4 page 7 Information about image buffer 0 and image buffer 1 was added For more information see Hardware Implementation page 3 Information about FSM states was updated For more information see FSM Implementation page 6 1 3 Revision 2 0 The following is a summary of ...

Page 7: ...number of additions and multiplications However a trade off is required between the computation complexity and quality of the scaled image Based on the content awareness of the algorithm the image scaling algorithms are classified as adaptive image scaling and non adaptive image scaling Adaptive image scaling algorithms modify their interpolation technique based on whether the image has a smooth t...

Page 8: ...Introduction UG0651 User Guide Revision 4 0 2 Figure 1 Scale Up from 2x2 to 4x4 6FDOHG XS PDJH EHIRUH QWHUSRODWLRQ 6FDOHG XS PDJH DIWHU QWHUSRODWLRQ 2ULJLQDO PDJH ...

Page 9: ...caler the next line must be input only after the Line_Done_o signal goes high For a new frame the first two lines of the frame need to be input before the scaler starts processing the data The data stored in the image buffer is scaled to calculate the output data based on the nearest neighbor algorithm When downscaling the height of the image the next input line to the scaler must begin with the p...

Page 10: ... to design SYS_CLK_I Input System clock DATA_In_i Input g_DATA_BITWIDTH g_CHANNELS 1 0 Input data to scaler DATAIn_VLD_i Input Set when input data is valid Start_i Input Scaler start signal To be set to high before loading a new frame PDJH XIIHU 6FDOHU 6FDOH DFWRUBL 6FDOH DFWRUBL 2XWSXW 5HVBL 2XWSXW 5HVBL QSXW 5HVBL 6WDUW 6 6B B Q5 6 7B 1 W LQH XIIB5G GGU XIIB5 XIIB5G DWD RQWURO 60 XIIB U GGU XIIB...

Page 11: ...TWIDTH 1 0 Indicates the pixel number of the source image from which the next line is to be dumped into the scaler image buffer When downscaling height wise this signal indicates the next line in sequence DATA_OUT_o Output g_DATA_BITWIDTH g_CHANNELS 1 0 Scaled data output DATAOut_VLD_o Output Sets when output data is a valid register and describes the output of the scaler line_ready Input Set when...

Page 12: ...he FSM moves to WAIT_STATE in the next cycle WAIT_STATE The FSM moves to DATAOUT state in the next cycle DATAOUT The output pixel is calculated based on the horizontal counter vertical counter and scaling factors The horizontal and vertical counters are updated and the read address and read enable signal for reading from one of the two image buffers is generated On completion of processing of one ...

Page 13: ...s that can be configured according to the application Table 3 Testbench Configuration Parameters Name Description CLKPERIOD Clock period IN_HEIGHT Height of the input image IN_WIDTH Width of the input image OUT_HEIGHT Height of the output frame OUT_WIDTH Width of the output frame IMAGE_FILE_NAME Input file name G2XW G2XW G2XW G2XW G2XW 6 6B BL 7 B QBL OLQHBUHDG 7 B287BR 7 2XWB9 BR OLQHBGRQHBR 1 WO...

Page 14: ...nd Create Design Right click Create SmartDesign Testbench and click Run as shown in the following figure Figure 5 Create SmartDesign Testbench 2 Enter a name for the SmartDesign testbench in the dialog box and click OK Figure 6 Create New SmartDesign Testbench Dialog Box A SmartDesign testbench is created and a canvas appears to the right of the Design Flow pane ...

Page 15: ...ore onto the SmartDesign testbench canvas Figure 7 Scaler The core appears on the canvas as shown in the following figure Figure 8 Scaler Core on SmartDesign Testbench Canvas 4 Select all the ports of the core right click and then click Promote to Top Level as shown in the following figure Figure 9 Promote to Top Level Option ...

Page 16: ...g figure Figure 10 Scaler Ports Promoted to Top Level 5 From the SmartDesign toolbar click the Generate Component highlighted in the following figure Figure 11 Generate Component 6 In the Files window right click the simulation directory and click Import files as shown in the following figure Figure 12 Import Files Option ...

Page 17: ...owing path Project_name component Microsemi SolutionCore Scaler 2 0 0 Stimulus To import a different file browse to the folder containing the image file and click Open Figure 13 Input File Selection The imported file is listed under simulation as shown in the following figure Figure 14 Input File in Simulation Directory 8 In the Stimulus Hierarchy expand Work and right click Scaler_test Scaler_tb ...

Page 18: ... in the DO file use the run all command in the transcript window to complete the simulation After the simulation is completed the testbench output image file appears in the simulation folder 3 6 Resource Utilization The scaler is implemented in the SmartFusion 2 system on chip SoC FPGA M2S150T 1FC1152 package The following table lists the resources used by the FPGA Table 4 Resource Utilization Rep...

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