Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
58
3.6.4.1
ADR
Generate PC-relative address.
3.6.4.1.1
Syntax
ADR{cond} Rd, label
where:
•
cond
is an optional condition code, see
.
•
Rd
is the destination register
•
label is a PC-relative expression. See
3.6.4.1.2
Operation
ADR generates an address by adding an immediate value to the PC, and writes the result to the
destination register.
ADR provides the means by which position-independent code can be generated, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the
address you generate is set to 1 for correct execution.
Values of
label
must be within the range of -4095 to +4095 from the address in the PC.
Note:
You may have to use the .W suffix to get the maximum offset range or to generate addresses that are not
word-aligned. See
3.6.4.1.3
Restrictions
Rd
must not be SP and must not be PC.
3.6.4.1.4
Condition flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
3.6.4.2
LDR and STR, Immediate Offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
3.6.4.2.1
Syntax
op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
•
op
is either LDR (load register) or STR (store register)
•
type
is one of:
•
B: unsigned byte, zero extend to 32 bits on loads.
•
SB: signed byte, sign extend to 32 bits (LDR only).
•
H: unsigned halfword, zero extend to 32 bits on loads.
•
SH: signed halfword, sign extend to 32 bits (LDR only).
•
-: omit, for word.
•
cond
is an optional condition code; see