RTC System
UG0331 User Guide Revision 15.0
604
The configuration bits in the mode registers should not be changed while the RTC is operational. The
Alarm and Compare registers can be written by disabling the alarm (bit 2), as explained in the
18.2.2.2.1 Clock Source to RTCCLK
The MSS clock controller supplies three clock sources to RTCCLK:
•
Crystal oscillator 32.767 KHz
•
1 MHz oscillator
•
50 MHz oscillator
The prescaler should be programmed to derive a 1 Hz signal. Therefore, for the 32.767 KHz clock, the
prescaler should be programmed to 32768 (actual value is N
1, that is, 32767). Microsemi recommends
that the lowest clock frequency source available is used because this reduces the power consumption;
the MSS SYSREG provides the clock selection logic.
18.2.3
Details of Operation
The following sections describe the details of operation of the RTC:
•
Day of the Week and Week Counter
•
RTC_MATCH Status Bit and Output
•
RTC_WAKEUP Status Bit
•
RTC_WAKEUP Output
18.2.3.1 Day of the Week and Week Counter
The Calendar counter also keeps track of the days within the weeks, and the weeks in a year. These
needs are to be set correctly before starting the RTC to match the day of the week and week for the
current date and time. The day of the week counter increments from 1 to 7 and the week counter is
incremented as the day of week goes from 7 to 1.
18.2.3.2 RTC_MATCH Status Bit and Output
The RTC_MATCH status bit and output is asserted whenever the Alarm system is enabled and a match
occurs. In Calendar mode, it is asserted for a 1 second period while the alarm condition is valid. The
output is synchronous to the rising edge of RTCCLK. The RTC_MATCH output signal can also be driven
to the fabric.
18.2.3.3 RTC_WAKEUP Status Bit
The RTC_WAKEUP status bit is asserted whenever the Alarm system (refer to alarm_enable in
page 610) is enabled and a match occurs. The bit stays set until cleared by writing to the
control register clear wake-up bit.
18.2.3.4 RTC_WAKEUP Output
The RTC_WAKEUP output is asserted whenever the Alarm system is enabled (alarm_enable), the mode
wake_enable (
page 611) is set and a match occurs by the RTCCLK rising edge. The bit stays
set until cleared by writing to the control register clear wakeup bit. The output de assertion is immediate
and synchronous to the PCLK.
The RTC_WAKEUP output can be routed to the fabric through the fabric interface interrupt controller
(FIIC) block in MSS and can be used by a soft microcontroller or a state machine implemented in the
fabric. It can also be routed to the Cortex-M3 processor nested vectored interrupt controller (NVIC) or it
can be routed to the system controller. The RTC_WAKEUP_CR in the SYSREG block provides masking
for the RTC_WAKEUP interrupt to the fabric, the Cortex-M3 processor, and the system controller.