CAN Controller
UG0331 User Guide Revision 15.0
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When enabled, CAN ports are configured to connect to SmartFusion2 multi-standard I/Os (MSIOs) by
default. CAN signals can also be configured to interface with the FPGA fabric and the MSS general
purpose inputs/outputs (GPIOs). The CAN configurator within Libero SoC allows selection from among
the fabric, MSIOs, and GPIOs.
Note:
The MSIOs allocated to the CAN instance are shared with other MSS peripherals. These shared I/Os are
available to connect to the MSS GPIOs and other peripherals when the CAN instance is disabled or if the
CAN instance ports are only connected to the FPGA fabric. Refer to the
for more details.
12.2.2
Transmit Procedures
The CAN controller provides 32 transmit message holding buffers. An internal priority arbiter selects the
message according to the chosen arbitration scheme. Upon transmission of a message or message
arbitration loss, the priority arbiter re-evaluates the message priority of the next message. The following
figure gives an overall view of the transmit message buffers.
Figure 167 •
Transmit Message Buffers
Two types of message priority arbitration are supported. The type of arbitration is selected using the
configuration register. Following are the arbitration types:
•
Round Robin
: Buffers are served in a defined order: 0-1-2... 31-0-1... A particular buffer is only
selected if its TxReq flag is set. This scheme guarantees that all buffers receive the same probability
to send a message.
•
Fixed Priority
: Buffer 0 has the highest priority. This way it is possible to designate buffer 0 as the
buffer for error messages and it is guaranteed that they are sent first.
Note:
RTR message requests are served before transmit message buffers are handled. For example,
RTRreq0, RTRreq31, TxMessage0, TxMessage1, and TxMessage31.
12.2.2.1 Procedure for Sending a Message
1.
Write message into an empty transmit message holding buffer. An empty buffer is indicated by the
TxReq that is equal to zero.
2.
Request transmission by setting the respective TxReq flag to 1.
3.
The TxReq flag remains set as long as the message transmit request is pending. The content of the
message buffer must not be changed while the TxReq flag is set.
4.
The internal message priority arbiter selects the message according to the chosen arbitration
scheme.
5.
Once the message is transmitted, the TxReq flag is set to zero and the tx_msg interrupt status bit is
asserted
RX
TxReq
TxReq
TxReq
TxReq
TX
TX_EN_N
APB_1 Bus
External
Transceiver
Chip
CAN Framer
TxMessage0
TxMessage1
TxMessage2
TxMessage31
Priority
Arbiter
APB Slave
Interface