Ethernet MAC
UG0331 User Guide Revision 15.0
397
0x108
R/W
0x0
This is incremented for each frame that experiences 16
collisions during the transmission and is aborted.
0x10C
R/W
0x0
This is incremented by the number of collisions experienced
during the transmission of a frame.
0x110
R/W
0x0
This is incremented each time a valid PAUSE MAC control
frame is transmitted and honored.
0x114
R/W
0x0
This is incremented each time PAUSE frame is honored.
0x118
R/W
0x0
This is incremented for each oversized transmitted frame with
an incorrect FCS value.
0x11C
R/W
0x0
This is incremented for each valid sized packet with an incorrect
FCS value.
0x120
R/W
0x0
This is incremented for each valid size frame with a Type Field
signifying a Control frame.
0x124
R/W
0x0
This is incremented for each oversized transmitted frame with a
correct FCS value.
0x128
R/W
0x0
This is incremented for each frame which is less than
64 bytes with a correct FCS value.
0x12C
R/W
0x0
This is incremented for each frame which is less than
64 bytes, with an incorrect FCS value.
0x130
RO
0x0
This indicates the transmit and receive counters and the
receive counters carry the bits. The carry register bits are
cleared on carry register write when the respective bit is
asserted.
0x134
RO
0x0
This indicates the transmit counters carry bits. The carry
register bits are cleared on carry register write when the
respective bit is asserted.
0x138
R/W
0xFE01FFFF The rollover condition of each transmit and receive counter and
receive counters can be discreetly masked from causing an
interrupt by internal masking.
0x13C
R/W
0xFFFFF
The rollover condition of each transmit counter can be
discreetly masked from causing an interrupt by internal
masking.
Table 338 •
EMAC M-SGMII Register Map
Register name
Address
Offset
Register
Type
Reset Value Description
0x00
R/W
0x0
This enables the loopback and the auto negotiation.
The PHY address for the M-SGMII is 0x1E.
0x01
RO
0x0001
This enables the MF PREMABLE suppression enable.
This indicates the auto negotiation complete, associated
PHY auto negotiation ability and link status.
The PHY address for the M-SGMII is 0x1E.
RESERVED
0x02
R/W
0x0
Reserved
Table 337 •
EMAC PE-MSTAT Transmit Counters Register Map
(continued)
Register
Name
Address
Offset
Register
Type
Reset Value Description