Model Configurations
2020 Microchip Technology Inc.
DS50002997A-page 18
FIGURE 5-4:
Power Stage Subsystem Selection.
5.3
CONTROLLER
The model contains three controller configurations: Steady-State Model, Discrete-Time
Domain Model, and Processor-In-the-Loop. The Steady-State Model configuration
provides quick startup and transient response in order to reach a steady state without
running through soft-start at startup or be slowed down by the PI controllers during
transient events. This is useful for thermal and efficiency simulations. Additionally, this
configuration operates in the continuous-time domain.
The Discrete-Time Domain Model configuration operates at an update rate of 35 kHz.
The model includes all the controls features of the Vienna PFC reference design except
for the in-rush relay control, protection, and diagnostics. The model's control behavior
and timing are strongly correlated to that of the reference design. However, the
simulation runs slower than the Steady-State Model configuration.
The Processor-In-the-Loop configuration allows the control algorithm to run on the
dsPIC33CH512MP506 DP Plug-In Module (PIM) via a USB connection. This enables
development and debugging of the control algorithm on the target processor with the
power stage and sensing simulation in PLECS. PIL software is provided with the
Vienna PFC PLECS model package for flashing into the dsPIC DSC Master and Slave
cores.
FIGURE 5-5:
Controller.
