2011-2015 Microchip Technology Inc.
DS40001609E-page 83
PIC16(L)F1508/9
8.0
POWER-DOWN MODE (SLEEP)
The Power-down mode is entered by executing a
SLEEP
instruction.
Upon entering Sleep mode, the following conditions exist:
1.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
2.
PD bit of the STATUS register is cleared.
3.
TO bit of the STATUS register is set.
4.
CPU clock is disabled.
5.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6.
Timer1 and peripherals that operate from
Timer1 continue operation in Sleep when the
Timer1 clock source selected is:
•
LFINTOSC
•
T1CKI
•
Timer1 oscillator
7.
ADC is unaffected, if the dedicated FRC oscillator
is selected.
8.
I/O ports maintain the status they had before
SLEEP
was executed (driving high, low or high-
impedance).
9.
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• CWG, NCO and CLC modules using HFINTOSC
I/O pins that are high-impedance inputs should be
pulled to V
DD
or V
SS
externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See
13.0 “Fixed Voltage Reference (FVR)”
for more
information on this module.
8.1
Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin, if enabled
2.
BOR Reset, if enabled
3.
POR Reset
4.
Watchdog Timer, if enabled
5.
Any external interrupt
6.
Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to
6.12 “Determining the Cause of a Reset”
When the
SLEEP
instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the
SLEEP
instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP
instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following
SLEEP
is not desirable, the user
should have a
NOP
after the
SLEEP
instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs
before
the execution of a
SLEEP
instruction
-
SLEEP
instruction will execute as a
NOP
.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs
during or after
the execu-
tion of a
SLEEP
instruction
-
SLEEP
instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the
SLEEP
instruction completes. To
determine whether a
SLEEP
instruction executed, test
the PD bit. If the PD bit is set, the
SLEEP
instruction
was executed as a
NOP
.
