
Board Layout and Schematics
2016 Microchip Technology Inc.
DS50002505A-page 57
FIGURE A-8:
POWER MODULE STAGE SCHEMATIC (SHEET 2 OF 6)
P
VFO
15V
M3_L
M1_H
VCC(UH)
VS(M2)
VCC(VH)
VS(M3)
VCC(WH)
I
15V_PFC
V_M3
V_M1
M2
VDD_PFC
VBUS
GND_DIG
M1_L
M2_L
VS(M1)
VB(U)
VB(V)
M2_H
VB(W)
M3_H
GND_DIG
GND_DIG
15V
IBUS_SHUNT-
GND_DIG
IBU
GND_DIG
N
D16
SS1P3L
GND_DIG
M1
M3
VDD_EXT
N
15V
AVDD_PFC
M3
M2
M1
GND_DIG
GND_DIG
2
3
1
VDD_EXT
GND_DIG
SML4747
D14
M3
IBU
IBU
I
V_M1
V_M2
VCC(WH)
VS(M3)
VS(M2)
IBU
GND_DIG
M1
M2
D15
BAT17
GND_DIG
+3.3V_DIG
REC_NEUTR
V_M3
V_M2
+3.3V_ANA
VB(W)
VCC(VH)
VB(V)
VCC(UH)
VS(M1)
VB(U)
1
3
2
15V
3FB
2GND
4
EN
5
V
IN
6
SW
1
BOOST
GND_DIG
GND_DIG
GND_DIG
BP2
BP1
2GND
1
V
IN
3
V
OUT