Microchip Technology dsPIC30F6010, Datasheet

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2004 Microchip Technology Inc.
Advance Information
DS70119B-page 97
dsPIC30F6010
16.3 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN =
1
). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MS bit,
even if SSx had been de-asserted in the middle of a
transmit/receive.
16.4 SPI Operation During CPU Sleep
Mode
During Sleep mode, the SPI module is shut-down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5 SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL =
0
, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL =
1
, the
module will stop when the CPU enters Idle mode.