Microchip Technology dsPIC24 series Family Reference Manual Download Page 9

 2006-2019 Microchip Technology Inc.

DS30009711C-page 9

I/O Ports with PPS

4.0

PERIPHERAL PIN SELECT

A major challenge in general purpose devices is providing the largest possible set of peripheral
features while minimizing the conflict of features on I/O pins. The challenge is even greater on
low pin count devices. In an application where more than one peripheral is needed to be
assigned to a single pin, inconvenient work arounds in application code or a complete redesign
may be the only option.
Peripheral Pin Select configuration provides an alternative to these choices by enabling users
peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout
options available on a particular device, users can better tailor the microcontroller to their entire
application, rather than trimming the application to fit the device.
The Peripheral Pin Select configuration feature operates over a fixed subset of digital I/O pins.
Users may independently map the input and/or output of most digital peripherals to any one of
these I/O pins. Peripheral Pin Select is performed in software and generally does not require the
device to be reprogrammed. Hardware safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has been established. 

4.1

Available Pins

The Peripheral Pin Select feature is used with a range of pins. The number of available pins is
dependent on the particular device and its pin count. Pins that support the Peripheral Pin Select
feature include the designation, “RPn”, in their full pin designation, where “RP” designates a
remappable peripheral and “n” is the remappable pin number. If the pin supports only the input
function Peripheral Pin Select feature, then it will be designated as “RPIn”. For more details, refer
to the device pinout in the respective device data sheet. 

4.2

Available Peripherals

The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These
include general serial communications (UART and SPI), general purpose timer clock inputs,
timer-related peripherals (input capture and output compare) and external interrupt inputs. 
In comparison, some digital only peripheral modules are not currently included in the Peripheral
Pin Select feature. This is because the peripheral’s function requires special I/O circuitry on a
specific port and cannot be easily connected to multiple pins. These modules include I

2

C,

specialty communication (Ethernet and USB), Change Notification (CN) inputs, RTCC alarm
output and all modules with analog inputs, such as the A/D Converter.
A key difference between remappable and non-remappable peripherals is that remappable
peripherals are not associated with a default I/O pin. The peripheral must always be assigned to
a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always
available on a default pin, assuming that the peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital
I/O and digital communication peripherals associated with the pin. Priority is given regardless of
the type of peripheral that is mapped. Remappable peripherals never take priority over any
analog functions associated with the pin.

Note:

Some devices do not have this feature. Please refer to the specific device data
sheet for more details.

Summary of Contents for dsPIC24 series

Page 1: ...following topics 1 0 Introduction 2 2 0 I O Port Control Registers 3 3 0 Peripheral Multiplexing 7 4 0 Peripheral Pin Select 9 5 0 Port Descriptions 19 6 0 Change Notification CN Pins 19 7 0 Register...

Page 2: ...als Figure 1 1 shows a block diagram of a typical I O port This block diagram does not take into account peripheral functions that may be multiplexed onto the I O pin Figure 1 1 Dedicated Port Structu...

Page 3: ...ify Write RMW operations There fore a write to a port implies that the port pins are read the value is modified and then written back to the port data latch Care should be taken when Read Modify Write...

Page 4: ...is 0 then the pin is configured for a normal digital output ODC bit is valid only for output pins After a Reset the status of all the bits of the ODCx register is set to 0 The open drain feature allo...

Page 5: ...t is cleared x Bit is unknown bit 15 0 TRISx 15 0 PORTx Data Direction Control bits 1 1 The pin is an input 0 The pin is an output Note 1 Refer to the specific device data sheet for the actual impleme...

Page 6: ...bit 15 0 LATx 15 0 PORTx Data Latch bits 1 1 The latch content is 1 0 The latch content is 0 Note 1 Refer to the specific device data sheet for the actual implementation R W 0 R W 0 R W 0 R W 0 R W 0...

Page 7: ...e peripheral functions may be multiplexed on each I O pin The priority of the peripheral function depends on the order of the pin description in the pin diagram of the specific product data sheet Figu...

Page 8: ...Software Input Pin Control Some of the functions assigned to an I O pin may be input functions that do not take control of the pin output driver An example of one such peripheral is the input capture...

Page 9: ...ates a remappable peripheral and n is the remappable pin number If the pin supports only the input function Peripheral Pin Select feature then it will be designated as RPIn For more details refer to t...

Page 10: ...ch Read PORTx Read TRISx n 0 WR TRISx Peripheral 2 Output Enable I O Peripheral n Output Enable PIO Module Output Multiplexers Output Function Read LATx 0 1 Peripheral Input Q Peripheral 1 Output Enab...

Page 11: ...ociated with a peripheral dictates the pin it will be mapped to The RPINRx reg isters refer to Register 4 3 and Table 4 1 contain sets of 6 bit fields with each set associated with one of the remappab...

Page 12: ...pture 2 IC2 RPINR7 13 8 IC2R 5 0 Input Capture 3 IC3 RPINR8 5 0 IC3R 5 0 Input Capture 4 IC4 RPINR8 13 8 IC4R 5 0 Input Capture 5 IC5 RPINR9 5 0 IC5R 5 0 Output Compare Fault A OCFA RPINR11 5 0 OCFAR...

Page 13: ...is mapped to the pin see Table 4 1 and Figure 4 3 The peripheral outputs that support Peripheral Pin Selection have no default pins Since the RPORy registers reset to all 0 s the outputs are all disc...

Page 14: ...on 1 RPnR 5 0 Output Name NULL 0 The pin is an I O Port pin C1OUT 1 RPn tied to Comparator 1 Output C2OUT 2 RPn tied to Comparator 2 Output U1TX 3 RPn tied to UART1 Transmit U1RTS 4 RPn tied to UART1...

Page 15: ...e the unlock sequence should be performed by writing inline assembly or using built in functions provided by the MPLAB C30 C Compiler IOLOCK remains in one state until changed This allows all of the P...

Page 16: ...ral output to a particular pin does not automatically perform any other configuration of the pin s I O circuitry This means adding a pin selectable output to a pin may mean inadvertently driving an ex...

Page 17: ...p w3 n pop w2 n pop w1 Configure Input Functions Assign U1Rx To Pin RP0 RPINR18bits U1RXR 0 0 represents RP0 Assign U1CTS To Pin RP1 RPINR18bits U1CTSR 1 1 represents RP1 Configure Output Functions As...

Page 18: ...in bits 1 bit 7 6 Unimplemented Read as 0 bit 5 0 Input Function Bits 5 0 Assign Peripheral to Corresponding RPn Pin bits 1 Note 1 Here n represents the peripheral select input pin number 2 Here x rep...

Page 19: ...registers associated with the CN module The CNENx registers contain the CNxIE control bits where x denotes the number of the CN input pin The CNxIE bit must be set for a CN input pin to interrupt the...

Page 20: ...condition and set up the CN logic to detect the next pin change The current PORTx value can be compared to the PORT read value obtained at the last CN interrupt to determine the pin that changed The C...

Page 21: ...x3 Rx2 Rx1 Rx0 xxxx ODCx PORTx Open Drain Control bits 0000 Note 1 Refer to the specific device data sheet for the I O Ports register map details Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 B...

Page 22: ...pecifically for the dsPIC33 PIC24 families of devices but the concepts are pertinent and could be used with modification and possible limitations The current application notes related to the I O Ports...

Page 23: ...evision A August 2006 This is the initial released revision of this document Revision B May 2007 Added PPS section removed JTAG boundary scan section and added PPS SFR table Revision C March 2019 Upda...

Page 24: ...dsPIC33 PIC24 Family Reference Manual DS30009711C page 24 2006 2019 Microchip Technology Inc NOTES...

Page 25: ...TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology...

Page 26: ...5300 China Xian Tel 86 29 8833 7252 China Xiamen Tel 86 592 2388138 China Zhuhai Tel 86 756 3210040 ASIA PACIFIC India Bangalore Tel 91 80 3090 4444 India New Delhi Tel 91 11 4160 8631 India Pune Tel...

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