7.
Appendix
7.1
Schematic
Figure 7-1. ATtiny1607 Curiosity Nano Schematic
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
2
of
4
A
T
ti
n
y1
60
7
C
u
ri
os
it
y
N
an
o
09
.0
5.
20
19
AT
tin
y1
60
7_
C
uri
os
it
y_
N
an
o_
Tar
ge
t_
M
C
U
.S
ch
D
oc
Proj
ect
Tit
le
PCB
Ass
emb
ly N
umb
er:
PCBA
Revis
ion:
File:
PCB
Numb
er:
PC
B
Re
vi
si
on
:
Desig
ned
with
Dra
wn
By
:
M
ic
ro
ch
ip
N
or
w
ay
She
et
Tit
le
Targe
t MCU
Engineer:
ML, TF
A08-2979
2
Size
A
3
A09-3252
2
Page:
Date:
Alt
ium
.co
m
PA6
PA7
PB7_LED0
PB6
PB5
PB4
PC4_SW0
PC2_MOSI
PC1_MISO
PC0_SCK
PB0_SCL
PB1_SDA
PB2_TXD
GND
VCC_TARGET
100n
C200
PC3_SS
PC0_SCK
PC1_MISO
PC2_MOSI
PB0_SCL
PB1_SDA
PA2_RX1
PA1_TX1
PB6
PB5
PB4
PA3
PA4
PA5
PA6
PA7
1k
R203
1k
R20
3
U
SE
R
L
ED
VCC_TARGET
PC3_SS
GND
US
ER
B
UT
TON
PC4_SW0
PC5
1k 1k
R202
YELLOW
LED
SML-D12Y1WT86
2
1
D200
TS604VM1-035CR
1
3
4
2
SW200
GND
GND
GND
PB7_LED0
PC4_SW0
BLM18PG471SN1
L200
2.
2u
F
C205
GND
D
B
G
0
C
D
C
_
U
A
R
T
TX
RX
UART
CDC_TX
CDC_RX
DBG2
D
B
G
1
D
B
G
3
D
B
G
2
DEBUGGER CONNECTIONS
DBG1
DBG3
D
B
G
0
C
D
C
_
U
A
R
T
C
D
C
_
U
A
R
T
TX
RX
UART
D
B
G
1
D
B
G
3
D
B
G
2
DBG0
ATtiny1607
PA0/UPDI
PB7/GPIO2
PC4/GPIO1
NA
Signal
DBG0
DBG1
DBG2
DBG3
Interface
CD
C
TX
CD
C
RX
UAR
T R
X
UAR
T
TX
VTG
1.8
V-
5.
5V
V
O
F
F
I
D
_
S
Y
S
ID_SYS
VOFF
2.
2u
F
C205
GND
TA
RGE
T B
ULK
PC4_SW0
PB7_LED0
VBUS
PB3_RXD
PC5
PA0_UPDI
GND
C
D
C
R
X
3
CD
C
TX
4
D
B
G
1
5
D
B
G
2
6
0 TX
7
1
R
X
8
2 S
DA
9
3 S
C
L
1
0
4
M
OS
I
1
1
5
M
IS
O
1
2
6
S
C
K
1
3
7
S
S
1
4
GN
D
1
5
0
(T
X
)
1
6
1 (RX)
1
7
D
B
G
3
3
2
D
B
G
0
3
1
GN
D
3
0
V
C
C
2
9
P
W
M
3
2
4
A
D
C
2
2
3
A
D
C
1
2
2
A
D
C
0
2
1
GN
D
2
0
3
1
9
2
1
8
A
D
C
7
2
8
A
D
C
6
2
7
A
D
C
5
2
6
P
W
M
4
2
5
DEBUGGER
TARGET
ID
2
VOFF
3
3
RESERV
ED
1
VB
US
3
4
CNAN
O34-p
in
edg
e co
nne
ctor
J200
PB2_TXD
PB3_RXD
PB2_TXD
PB3_RXD
PA1_TX1
PA2_RX1
PA3
PA4
PA5
PA0_UPDI
ATtiny1607-MNR
ATtiny1607-MNR
P
A
2
1
P
A
3
/
C
L
K
I
2
G
N
D
3
V
C
C
4
P
A
4
5
P
A
5
6
PA
6
7
PA
7
8
PB
7
9
PB
6
10
PB
5
11
PB
4
12
P
B
3
1
3
P
B
2
1
4
P
B
1
1
5
P
B
0
1
6
P
C
0
1
7
P
C
1
1
8
PC
2
19
PC
3
20
PC
4
21
PC
5
22
RE
SE
T/
UP
DI
/P
A0
23
PA
1
24
P
A
D
2
5
U200
J203
J201
J204
J205
J206
ATtiny1607
J202
NC
VCC_EDGE
VCC_EDGE
NOT
E o
n U
ART
/C
DC:
RX
/T
X
on
the
h
ea
de
r
de
no
te
s
th
e
inp
ut/
out
pu
t d
ire
ct
io
n o
f
the
si
gn
al
re
sp
ec
ti
ve
to
it
's
s
ou
rc
e.
CD
C
TX
is
ou
tp
ut
f
ro
m
th
e
DE
BU
GG
ER
.
CD
C
RX
is
in
put
to
th
e
DE
BU
GG
ER
.
TX
is
ou
tp
ut
f
ro
m
th
e
TA
RG
ET
d
ev
ic
e.
RX
is
in
pu
t to
the
T
AR
GE
T
de
vi
ce
.
NO
TE
o
n
I2
C:
No
p
ul
l-
up
s
on
b
oa
rd
. Pu
ll
-u
ps
s
ho
ul
d
be
mo
un
te
d
cl
os
e
to
s
la
ve
d
ev
ic
e(
s)
.
ATtiny1607 Curiosity Nano
Appendix
©
2019 Microchip Technology Inc.
User Guide
DS50002897A-page 21