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Register Description
IF2008/PCIe / IF2008E
Clock splitter:
Bit 3 Bit 2 Bit 1 Bit 0 Clock frequency timer 1
Bit 7 Bit 6 Bit 5 Bit 4 Clock frequency timer 2
Bit 11 Bit 10 Bit 9 Bit 8 Clock frequency timer 3
0
0
0
0
24 MHz
0
0
0
1
24 MHz / 2
0
0
1
0
24 MHz / 4
0
0
1
1
24 MHz / 8
0
1
0
0
24 MHz / 16
0
1
0
1
24 MHz / 32
0
1
1
0
24 MHz / 64
0
1
1
1
24 MHz / 128
1
0
0
0
24 MHz / 256
1
0
0
1
24 MHz / 512
1
0
1
0
24 MHz / 1024
1
0
1
1
24 MHz / 2048
1
1
0
0
24 MHz / 4096
1
1
0
1
24 MHz / 8192
1
1
1
0
24 MHz / 16384
1
1
1
1
24 MHz / 32768
Fig. 33: Timer clock splitter
i
Bit 12 to Bit 15 are reserved.
10.13 ADC
Base addr. ADC channel Value
Access
+ 20h
1
0 to 65535
only read access
+ 22h
2
0 to 65535
only read access
Fig. 34: Base addresses for ADC
10.14 Status
Base addr. + 24h (only read access)
Bit
Function
0
1 = Encoder 1: 1st reference mark crossed
1
1 = Encoder 1: 2nd reference mark crossed
2
1 = Encoder 2: 1st reference mark crossed
3
1 = Encoder 2: 2nd reference mark crossed
4
0 = Transmitter ready for new data transfer
1 = Transmitter is occupied
5
0 = No extension module with sensor 5 / 6 available
1 = Extension module with sensor 5 / 6 available
6
0 = No extension module for external I/O available
1= Extension module for external I/O available
7
0 = No extension module with ADC available
1 = Extension module with ADC available
8 – 13
FPGA version
14 – 15
Hardware version
Fig. 35: Status
