Measurement Computing Data Translation DT3010 Series, User Manual, Page: 129 / 232

Chapter 6
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The host computer must pack two output samples (an even and an odd sample) into each
transfer to the DT3010 Series board. The even sample is written to the output FIFO first,
followed by the odd sample. If the analog output channel list contains two DACs, the even
samples (0, 2, 4, and so on) are written to channel entry 0 in the analog output channel list; the
odd samples (1, 3, 5, and so on) are written to channel entry 1 in the analog output channel list.
If the analog output channel list contains one DAC, all the samples are written to the DAC,
alternating between even and odd samples.
Note that for continuously-paced analog output operations, the data from the circular buffers
in host computer memory can wrap multiple times. Data is output from each of the buffers on
the queue; when no more buffers are on the queue, the operation stops.
In waveform generation mode, the data from a single circular buffer is written once to the
output FIFO on the board (wrap mode is single); the board then continuously outputs the
data. That is, once all the data in the buffer is written to the output FIFO on the board, the host
computer is finished transferring data; the board recycles the data in the output FIFO without
using the bandwidth of the PCI bus or host processor, and the process repeats continuously
until you stop the operation.
Error Conditions
DT3010 Series boards can report an output FIFO underflow error to the host computer. This
error indicates that the analog output data was not being transferred fast enough across the
PCI bus from the host computer to the output FIFO on the board.
If the D/A output clock occurs while the output FIFO is empty, an error is not reported since
the most likely cause is that the host computer has no more data to output; in this case, the last
value received from the host computer is output by the specified DACs continuously until the
board is powered down or new data becomes available. If, however, the host does an
additional write to the output FIFO (after the D/A output clock occurred while the output
FIFO was empty), the data is written to the DACs and the output FIFO Underflow error is
reported. This error has no effect on board operation; the host computer can clear this error.
To avoid this error, ensure that the host computer provides data to the output FIFO faster than
the DACs are converting the data. You can read the value of the output FIFO counter to
determine how many samples are in the output FIFO.
If this error condition occurs, the host computer stops transferring data to the board and the
board continues to output the last data transferred to it by the host computer.