Maxim Dallas Semiconductor DS3171, General Description Manual, Page: 64 / 234

DS3171/DS3172/DS3173/DS3174
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The CLAD MODE inputs to the clock rate adapter are composed of CLAD[3:0] control bits (located in the GL.CR2
Register) which determines which pins are input and output and which clock rate is on which pin. When
CLAD[3:0]=00XX, the PLL circuits are disabled and the signals on the input clock pins are used as the internal LIU
reference clocks. When CLAD[3:0]=(01XX or 10XX or 11XX), none, one or two PLL circuits are enabled to
generate the required clocks as determined by the CLAD[3:0] bits and the framing mode (FM[2:0]) and the line
mode (LM[2:0]) control bits. If a clock rate is not required on the CLAD output clock pins or for a reference clock for
any of the LIU, then the PLL used to generate that clock is disabled and powered down.
For example, in a design that only has the ports running at DS3 rates, then CLAD[3:0] can be set = 0100 and the
DS3 clock signal on the CLKA pin will be used as the DS3 LIU reference clock and no PLL circuit will be disabled.
Table 10-11. CLAD IO Pin Decode
GL.CR2 .
CLAD[3:0]
CLKA PIN CLKB PIN CLKC PIN
00 XX DS3 clock input E3 clock input STS-1 clock input
01 00 DS3 clock input Low output Low output
01 01 DS3 clock input E3 clock output Low output
01 10 DS3 clock input Low output STS-1 clock output
01 11 DS3 clock input STS-1 clock output E3 clock output
10 00 E3 clock input Low output Low output
10 01 E3 clock input DS3 clock output Low output
10 10 E3 clock input Low output STS-1 clock output
10 11 E3 clock input STS-1 clock output DS3 clock output
11 00 STS-1 clock input Low output Low output
11 01 STS-1 clock input E3 output Low output
11 10 STS-1 clock input Low output DS3 clock output
11 11 STS-1 clock input DS3 clock output E3 clock output
10.4.2 8 kHz Reference Generation
The global 8KREF signal is used to generate the one-second-reference signal by dividing it by 8000. This signal
can be derived from almost any clock source on the chip as well as the general-purpose IO pin GPIO4. The port
8KREF signal can be sourced from either the global 8KREF signal or from the transmit or receive port clock or from
the receive 8KREF signal. The minimum input frequency stability of the 8KREF input pin is +/- 500 ppm.
The global 8KREF signal can come from an external 8000 Hz reference connected to the GPIO4 general-purpose
IO pin by setting the
GL.CR2. G8KIS bit. The global 8KREF signal can be output on the GPIO2 general-purpose IO
pin when the GL.CR2 .G8KOS bit is set.
The global 8KREF signal can be derived from the CLAD PLL or pins or come from any of the port 8KREF signals
by clearing
GL.CR2. G8KIS bit and selecting the source using the GL.CR2. G8KRS[2:0] bits.
The port 8KREF signal can be derived from the transmit clock input pin or from the receive LIU or input clock pin.
The
PORT.CR3 .P8KRS[1:0] bits are used to select which source.
The 8KREF 8.000 kHz signal is a simple divisor of 44736 kHz (DS3 divided by 5592) or 33368 kHz (E3 divided by
4296). The correct divisor for the port 8KREF source is selected by the mode the port is configured for. The CLAD
clock chosen for the clock source selects the correct divisor for the global 8KREF. The 8KREF signal is only as
accurate as the clock source chosen to generate it.
Table 10-12 lists the selectable sources for global 8 kHz reference sources.