DS3171/DS3172/DS3173/DS3174
63
and automatic FEBE is enabled. Transmit clock comes from the CLAD CLKA pin. The pin inversion on all pins is
disabled.
Individual blocks are reset and powered down when not used determined by the settings in the line mode bits
LM[2:0] and framer mode bits
FM[2:0].
10.4 Global Resources
10.4.1 Clock Rate Adapter (CLAD)
The clock rate adapter is used to create multiple clocks for LIU reference clocks or transmit clocks from a single
clock reference input on the CLKA pin. The clock frequency applied to this pin must be at the DS3 (44.736 MHz),
E3 (34.368 MHz) and STS-1 (51.84 MHz) clock rates. Given one of these clocks the other two clocks will be
generated. The internally generated signals can be driven on output pins (CLKB and CLKC) for external use.
The receive LIU is supplied a reference clock from the CLAD. The receive LIU selects the clock frequency based
upon the mode the user selects via the FM bits. The CLAD output is also available as a transmit clock source if
selected via the
.CLADC register bit.
The user must supply at least one of the three rates (DS3, E3, STS-1) to the CLKA pin. The CLAD[3:0] bits inform
the PLL of the frequency applied to the pins. Selection of the output clock of the CLAD applied to the LIU and
optionally the transmitter is controlled by the FM bits (located in
). The CLAD allows maximum flexibility
to the user. The user may supply any of the three clock rates and use the CLAD to convert the rate to the particular
clock rate needed for his application.
Figure 10-6. CLAD Block
CLKA
CLKB
CLKC
DS3 clock
E3 clock
CC52 clock
CLAD
CLAD MODE
The clock rate adapter can also be disabled and all three clocks supplied externally using the CLKA, CLKB and
CLKC pins as clock inputs. When the CLAD is disabled, the three reference clocks DS3, E3 and STS-1 will need to
be applied to the CLKA, CLKB and CLKC pins, respectively. If any of the three frequencies is not required, it does
not need to be applied to the CLAD CLK pins.