MAX32660 User Guide
Maxim Integrated
Page 32 of 195
Table 4-10: ICC Cache Control Register
ICC Cache Control Register
ICC0_CACHE_CTRL
[0x0100]
Bits
Name
Access
Reset
Description
31:16
-
R/W
-
Reserved for Future Use
Do not modify this field.
16
ready
RO
-
Ready
This field is cleared by hardware anytime the cache as a whole is invalidated (including
a Power On Reset event). Hardware automatically sets this field to 1 when the
invalidate operation is complete and the cache is ready.
0: Cache Invalidate in process.
1: Cache is ready.
Note: While this field reads 0, the cache is bypassed and reads come directly from the
line fill buffer.
15:1
-
R/W
-
Reserved for Future Use
Do not modify this field.
0
enable
R/W
0
Enable
Set this field to 1 to enable the cache. Setting this field to 0 automatically invalidates
the cache contents. When this cache is disabled, reads are handled by the line fill
buffer.
0: Disable Cache
1: Enable Cache
Table 4-11: ICC Invalidate Register
ICC Invalidate Register
ICC0_INVALIDATE
[0x0700]
Bits
Name
Access
Reset
Description
31:0
-
WO
-
Invalidate
Any write to this register of any value invalidates the cache.
4.10
RAM Memory Management
This device has many features for managing the on-chip RAM. The on-chip RAM includes data RAM, an instruction cache
(ICC0), and the peripheral FIFOs.
4.10.1
On-Chip Cache Management
The MAX32660 includes an instruction cache controller for code fetches from the flash memory. The cache can be
enabled, disabled, and zeroized and the cache clock can be disabled by placing it in Light Sleep. Refer to section
4.10.2
RAM Zeroization
The GCR Memory Zeroize Control Register,
, allows clearing memory by the application. Zeroization writes
all zeros to memory.
The following RAM memories can be zeroized:
•
Data RAM
−
Zeroize the entire Data RAM by setting
sram_zero
bit to 1
•
Instruction Cache Controller Data and Tag RAM
−
Set
icache_zero
to 1 to zeroize the entire 16KB cache RAM and tag RAM
