Maxim Integrated MAX32660, User Manual

Page: 184 / 195

MAX32660 User Guide
Maxim Integrated Page 184 of 195
The application overhead required to left justify the transmit data can be eliminated by setting the tx_lj bit in the
SPIMSS_MODE register. When SPIMSS_MODE .tx_lj = 1, transmit data is always written by software or DMA to
SPIMSS_DATA in right justified form and hardware performs the left justify according to SPIMSS_MODE . numbits when the
shift register is loaded. For the 4-bit character example, when SPIMSS_MODE .tx_lj = 1, transmit data is written to
SPIMSS_DATA [3:0] and hardware shifts these to bits SPIMSS_DATA [15:12] when the shift register is loaded. The
SPIMSS_MODE .tx_lj bit has no effect on receive data which is always right justified.
14.3.5 SPI Master Configuration
Perform the following steps to configure SPI1 for master mode:
•
Set SPIMSS_CTRL .enable to 0 to disable the SPIMSS peripheral.
•
Enable SPI master mode by setting SPIMSS_CTRL .mode to 1.
•
Set the SPIMSS SPI1 pins to wired OR/open drain, if required, by setting SPIMSS_CTRL .wor to 1.
•
Set the slave select pin to an output by setting SPIMSS_CTRL .ss_io = 1
•
Configure the clock phase and polarity, if required, using the SPIMSS_CTRL .phase and SPIMSS_CTRL .clkpol bits.
•
Set the number of bits per character using the SPIMSS_MODE .numbits field.
•
Configure the Bit Rate Generator for the desired bit transmission rate. Refer to section SPIMSS Bit Rate Generator .
•
Load data in the Transmit FIFO to send to the slave or configure the Transmit and Receive DMA.
•
Enable SPI1 by setting the SPIMSS enable bit, SPIMSS_CTRL .enable, to 1.
•
Optionally force a SPIMSS data interrupt by setting SPIMSS_CTRL . str to 1.
The SPIMSS_CTRL .phase, SPIMSS_CTRL .clkpol and the SPIMSS_MODE .numbits fields must be consistent with the slave SPI
device for successful operation. The SPIMSS_MODE . ssv bit controls the asserted level for the slave select output pin,
SPI1_SS0. Set SPIMSS_MODE . ssv to 1 to set the slave select to active high. The typical SPI device uses an active low slave
select signal and the SPIMSS_MODE . ssv defaults to 0 for an active low slave select output.
14.3.6 SPI Slave Configuration
Perform the following steps to configure SPI1 for slave mode:
3. Disable the SPI1 by clearing the enable bit ( SPIMSS_CTRL .enable = 0)
4. Set SPI1 to slave mode, by setting the SPIMSS_CTRL .mode bit to 0.
5. Set SPIMSS_CTRL .wor to 0 for wired OR/open drain for all the SPIMSS (SPI1/I
2
S) I/O pins.
6. Set SPIMSS_CTRL .ss_io to 0 to set the slave select pin (SPI1_SS0) as an input.
7. Configure the clock phase and polarity, if required, using the SPIMSS_CTRL .phase and SPIMSS_CTRL .clkpol bits.
8. Set the number of bits per character using the SPIMSS_MODE .numbits field.
9. Load data in the Transmit FIFO to send to the master for the next communication or configure the Transmit and
Receive DMA.
10. Enable SPI1 by setting the enable bit, SPIMSS_CTRL .enable, to 1 to begin transmitting and receiving data.
The SPIMSS_CTRL .phase and SPIMSS_CTRL .clkpol bits and the SPIMSS_MODE .numbits field must be set to be consistent
with the SPI master. The SPIMSS_CTRL .str bit may be used, if desired, to force a start interrupt when the master SPI device
asserts the slave select pin, SPI1_SS0. The baud rate generator timer interrupt flag, SPIMSS_CTRL .birq, and the slave select
value bit, SPIMSS_CTRL .ssv, are not used in SPI slave mode. The SPI bit rate generator is not used in slave mode, so the
Mode Register, SPIMSS_MODE , does not need initialization.
If the slave has data to send to the master, the data should be written before the transaction starts (first edge of SCK after
the slave select pin, SPI1_SS0, is asserted). If the
SPIMSS_DATA register is not written prior to the slave transaction, the
SPI1_MISO pin will output whatever value was written last into the SPIMSS_DATA Register. Avoid this issue by loading the
transmit FIFO or configure transmit DMA prior to enabling SPI1.