MAX32660 User Guide
Maxim Integrated
Page 168 of 195
The DMA is configured using
Set
start
= 1 to begin a Master Mode transmission.
Do not modify the SPI timing registers while a SPI transaction is in progress. Modifying any SPI timing register while a SPI
transfer is in progress will result in an invalid SPI communication transaction.
To prevent a stall condition when in Master Mode, ensure that the transmit FIFO does not empty until the entire
transmission is complete.
13.3.12
SPI FIFOs
The Transmit FIFO hardware is 32 bytes deep. The write data width can be 8-, 16- or 32-bits wide. A 16-bit write queues a
16-bit word to the FIFO hardware. A 32-bit write queues two 16-bit words to the FIFO hardware with the least significant
word dequeued first. Bytes must be written to two consecutive byte addresses, with the odd byte as the most significant
byte, and the even byte as the least significant byte. The FIFO logic waits for both the odd and even bytes to be written to
this register space before dequeuing the 16-bit result to the FIFO.
The Receive FIFO hardware is 32 bytes deep. Read data width can be 8-, 16- or 32-bits. A byte read from this register
dequeues one byte from the FIFO. A 16-bit read from this register dequeues two bytes from the FIFO, least significant byte
first. A 32-bit read from this register dequeues four bytes from the FIFO, least significant byte first.
13.3.13
SPI Interrupts and Wakeups
The SPI supports multiple interrupt sources. Interrupt source events can come from the FIFOs, the SS and SR signals, and SPI
status. Status flags for each interrupt are set regardless of the state of the interrupt enable bit for that event. Each interrupt
flag field is set once when the condition is satisfied and remains set until cleared by the application. Write 1 to clear a
specific interrupt flag field.
The following FIFO interrupts are supported:
•
Transmit FIFO Empty
•
Transmit FIFO Level below threshold, where the level is set by firmware.
•
Receive FIFO Full
•
Receive FIFO Level above threshold, where the level is set by firmware.
•
Transmit FIFO Underrun (Slave mode only, Master mode stalls the clock)
•
Transmit FIFO Overrun
•
Receive FIFO Underrun
•
Receive FIFO Overrun (Slave Mode only, Master Mode will stall the clock)
Note: On the MAX32660 SPI0 use of the Transmit FIFO level interrupt is recommended to avoid the Transmit FIFO empty and
the TX FIFO underrun conditions from occurring in both Master or Slave mode operation.
The SPI supports interrupts for the internal state of the SPI as well as external signals. The following transmission interrupts
are supported:
•
SS Asserted or Deasserted
•
Transmission Complete
•
Slave Mode Transaction Aborted
•
Multi-Master Fault
