MAX32660 User Guide
Maxim Integrated
Page 141 of 195
Note for receive operations, the length of the DMA transaction (in bytes) must be an integer multiple of
.rxth.
Otherwise, the receive transaction will end with some data still in the RX FIFO, but not enough to trigger an interrupt to the
DMA, leaving the DMA transaction incomplete. One easy way to ensure this for all transaction lengths is to set burst size
to 1
.rxth = 1).
To enable DMA transfers, enable the TX DMA channel (
txen
) and/or the RX DMA channel (
rxen
).
for more information on configuring the DMA.
12.10
I
2
C Master Mode Transmit Operation
The peripheral operates in master mode when Master Mode Enable
mst
= 1. To initiate a transfer, the master
generates a START condition by setting
start
=1. If the bus is busy, it does not generate a START
condition until the bus is available.
A master can communicate with two slave devices without relinquishing the bus. Instead of generating a STOP condition
after communicating with the first slave, the master generates a Repeated START condition, or RESTART, by setting
restart
= 1. If a transaction is in progress, the master finishes the transaction before generating a
RESTART. The controller then transmits the slave address stored in the TX FIFO. The
.restart
bit is
automatically cleared to 0 as soon as the master begins a RESTART condition. The reception of a STOP condition clears any
pending RESTART.
.start
is automatically cleared to 0 after the master has completed a transaction and sent a STOP
condition.
The master can also generate a STOP condition by setting
stop
= 1.
If both START and RESTART conditions are enabled at the same time, a START condition is generated first. Then, at the end
of the first transaction, a RESTART condition is generated.
If both RESTART and STOP conditions are enabled at the same time, a STOP condition is not generated. Instead, a RESTART
condition is generated. After the RESTART condition is generated, both bits are cleared.
If START, RESTART, and STOP are all enabled at the same time, a START condition is first generated. At the end of the first
transaction, a RESTART condition is generated. The
.stop
bit is cleared and ignored.
A slave cannot generate START, RESTART, or STOP conditions. Therefore, when Master Mode is disabled, the
start
restart
.stop
bits are all cleared to 0.
Note: After starting a transfer,
.start = 1, changing the I
2
C configuration results in unpredictable
behavior.
12.11
I
2
C Master Mode Transmit Bus Arbitration
The I
2
C protocol supports multiple masters on the same bus. When the bus is free, it is possible that two masters might try
to initiate communication at the same time. This is a valid bus condition. If this occurs, only one master can remain in
master mode and complete its transaction. The other master must back off transmission and wait until the bus is idle. This
process is called bus arbitration.
To determine which master wins the arbitration, each master compares the data being transmitted on SDA to the value
observed on SDA. If the master attempting to transmit a 1 on SDA (that is, the master wants SDA to float) senses a 0
instead, that master concludes that it has lost arbitration because another master is transmitting a 0 onto SDA. It then
cedes the bus by switching off its SDA driver.
