MAX32600 User’s Guide
Analog Front End
8.4 DAC
Sample Count Mode
When using this DAC operating mode, the total number of sample code values that the DAC should pull from the FIFO to generate the pattern must be specified.
This sample count must be written to
. Once the DAC has pulled this number of samples from the FIFO, the DAC will halt and hold the last
output voltage.
Note that the sample count will normally be larger than the number of samples that can fit in the DAC FIFO (since the FIFO is only 16 levels deep for the 8-bit
DAC instances DAC2/DAC3, and only 32 levels deep for the 12-bit DAC instances DAC0/DAC1). To prevent gaps in the DAC waveform output, the application must
monitor the DAC FIFO status (either directly via CPU interrupt or indirectly using the PMU) and copy additional sample code values into the DAC FIFO when the
FIFO nears the empty state. This is done using the DAC FIFO Almost Empty programmable threshold and the DAC FIFO Almost Empty status flag (for use by the
PMU) and accompanying interrupt flag and interrupt enable (for use by the CPU).
If Interpolation Mode is being used, it is important to note that the Sample Count parameter only refers to the number of sample code values that the DAC pulls from
the FIFO. Using the interpolation function will increase the number of voltage values (each with a delay between them defined by the Rate Count parameter) that are
generated at the DAC output, but it does not change the effective Sample Count value.
Continuous Mode
This mode operates in the same manner as Sample Count Mode except that no sample count value is written. Instead, the DAC continues to pull values from the
FIFO (at a rate controlled by the Rate Count parameter) until the DAC is disabled, reset, or switched to a different operating mode. This mode is useful when the
application needs the DAC to continue to output a repeating voltage pattern indefinitely or until some condition occurs.
As with Sample Count Mode, the interpolation function can be used if needed, and it operates in the same manner.
8.4.4
Additional Topics
Certain DAC operating modes or application / system conditions require special handling or correction / compensation methods to achieve ideal voltage output
accuracy.
8.4.4.1
Reduced Power Level Modes for 12-bit DAC Instances
The two 12-bit DAC instances (DAC0 and DAC1) provide a number of lower-power modes that can be used to operate the DAC instance at less than full power. It is
important to note that while the current of the DAC can be adjusted using this setting, only the negative DAC output can have its impedance changed. As a result, at
any power level other than full power, the negative DAC output should be used instead of the positive one. To correct for this, all voltage output codes used by the
DAC should be corrected to:
(code used for low power) = 1 – (original DAC code used at full power)
Rev.1.3 April 2015
Maxim Integrated
Page 460
