MAX32600 User’s Guide
Memory, Register Mapping, and Access
3.4 AHB Bus Matrix and AHB Bus Interfaces
The Secure Key Storage Area consists of four V
RTC
-backed 32-bit registers:
, and
3.4
AHB Bus Matrix and AHB Bus Interfaces
This section details memory accessibility on the AHB bus matrix and the organization of AHB master and slave instances.
3.4.1
Core AHB Interface - I-Code
This AHB master is used by the ARM core for instruction fetching from the code space. This bus master has access to the main flash program memory and the main
system SRAM.
3.4.2
Core AHB Interface - D-Code
This AHB master is used by the ARM core for data fetches from the code space. This bus master has access to the main flash program memory, the information
block (when it is not locked), and the main system SRAM.
3.4.3
Core AHB Interface - System
This AHB master is used by the ARM core for other data read and write operations involving the system SRAM, the APB mapped peripherals (through the AHB-to-APB
bridge), and AHB mapped peripheral and memory areas.
3.4.4
AHB Master - Peripheral Management Unit (PMU)
The PMU bus master has access to all off-core memory areas (equivalent to the System plus D-Code) with the exception of the USB AHB memory mapped area.
The PMU bus master does not have access to the ARM Private Peripheral Bus area.
3.4.5
AHB Master - USB Endpoint Buffer Manager
The USB AHB bus master is used to manage endpoint buffers in the main system SRAM. It has access to the main system SRAM and flash main memory.
Rev.1.3 April 2015
Maxim Integrated
Page 28