MaximIntegrated 7-5
MAX31782 User’s Guide
Revision 0; 8/11
• Clears the I2CST_S .I2CBUSY flag to indicate that the I
2
C slave controller is not actively participating in the transfer
of data .
The detection of an ACK by the MAX31782 I
2
C slave controller indicates that the host wants to receive another byte of
data . The I
2
C slave controller maintains control of SDA following the ACK . The next byte to transmit needs to be loaded
into I2CBUF_S prior to the host starting to clock this next byte . However, data cannot be loaded into I2CBUF_S prior to
I2CBUSY being cleared, which indicates that all the bits in I2CBUF_S have been shifted onto SDA .
The detection of a NACK indicates that the host does not want to receive any additional data . The MAX31782 I
2
C slave
controller releases control of SDA following the reception of the NACK bit . After the NACK, the slave controller enters
idle state and monitors the I
2
C bus for a START or STOP condition .
7.1.7ReceivingData
The MAX31782 I
2
C slave controller enters data reception mode after receiving a matching slave address with the R/
W
bit set to a 0 . The steps of data reception are shown in
. The reception process begins when the I
2
C slave
controller detects the first rising edge of SCL . This first rising edge sets I2CBUSY and also clock the first bit (MSB) of
data from SDA into the data shift register .
When receiving data, the MAX31782 I
2
C slave controller uses a double buffer consisting of the I2CBUF_S register and
the shift register . This allows the I
2
C module to continue receiving data while the previous data byte is being processed .
After a complete byte (8 bits) of data are received, the I
2
C slave controller attempts to copy the received data from
the shift register to I2CBUF_S . There are two possible results from the I
2
C slave controllers attempt to copy the shift
register to I2CBUF_S .
1) If I2CBUF_S is empty, the I
2
C slave controller copies the data from the shift register into I2CBUF_S . The I2CRXI flag
is set to indicate a received byte is ready to be read . The setting of I2CRXI can generate an interrupt if enabled .
2) If I2CBUF_S is full, the data in the shift register cannot be copied into I2CBUF_S . This causes a receive overrun
condition . The receive overrun flag, I2CROI, is set, which can generate an interrupt if enabled . I2CBUF_S is full if it
was not read by software following the reception of a previous byte .
After receiving a byte of data and the I2CRXI flag being set, it is up to software to read I2CBUF_S prior to a second
byte being received . Reading the I2CBUF_S register returns the received data and also clears I2CBUF_S . As long as
the previous byte of data is read from I2CBUF_S before the next byte has completed, receive overrun does not occur .
When in receive overrun and the I2CROI bit is set, any new incoming data is not shifted into the I2C slave controller . The
controller responds to any bytes received with a NACK regardless of the setting of the I2CACK bit . The receive overrun
condition and the I2CROI flag can only be cleared by software reading the first byte received from I2CBUF_S . When
the receive overrun condition is cleared, the I
2
C slave controller copies the second byte that was received into I2CBUF,
and again set I2CRXI to indicate a byte of data was received . The I
2
C slave controller resumes its normal operation in
the next SCL clock cycle after I2CROI is cleared . To avoid losing any data, I2CROI must to be cleared prior to the first
SCL clock rising edge of the next byte .
After the 9th bit of any byte has been received, the I2CBUSY bit is cleared to indicate that the controller is no longer
participating in a data transaction . The value in I2CACK is transmitted to the host on the 9th SCL clock cycle, assuming
the I
2
C slave controller is not operating in receive overrun .
