Matrox Rapixo CL Pro, Installation And Hardware Reference, Page: 51 / 96

Auxiliary signals 51
Trigger
You can use as a trigger any of the auxiliary input signals (or auxiliary I/O signals
in input mode) of Matrox Rapixo CL Pro. A trigger signal can be used to initiate
image acquisition, or prompt an on-board event.
Each PSG has 4 trigger controllers. Each trigger controller can trigger the image
acquisition, the timers, and/or the synchronization signals of the PSG’s acquisition
path. Only one auxiliary signal per trigger controller can be programmed as a
trigger input signal. The auxiliary signals are restricted to specific trigger
controllers.
Timing requirements
When you use an auxiliary input signal as a trigger, the pulse width of the signal
must be at least 16 nsec (2 clock periods at 125 MHz).
To enable grabbing upon a trigger, use the MIL-Lite function MdigControl() with
M_GRAB_TRIGGER_STATE. To set the signal used to trigger the grab, use
MdigControl() with M_GRAB_TRIGGER_SOURCE. To start a timer upon a
trigger, use MdigControl() with M_TIMER_TRIGGER_SOURCE .
LVDS _ AU X_I N26
(M 4) _ AU X_I O
PSG 0 PSG 1
TTL _ AU X_I O _ 4
(M _ AU X_I O8)
OPTO _ AU X_I N0
(M _ AU X_I O _ 6)
LVDS _ AU X_I N2
(M _ AU X_I O10)
T
rigger
Contro
ll
er
0
MU
X
TTL _ AU X_I O _5
(M _ AU X_I O 9 )
OPTO _ AU X_I N1
(M _ AU X_I O 7 )
LVDS _ AU X_I N3
(M _ AU X_I O11)
T
rigger
Contro
ll
er
1
MU
X
TTL _ AU X_I O _ 6
(M _ AU X_I O2)
OPTO _ AU X_I N8
(M _ AU X_I O0)
LVDS _ AU X_I N10
(M _ AU X_I O4)
T
rigger
Contro
ll
er
2
MU
X
TTL _ AU X_I O _ 14
(M _ AU X_I O3)
OPTO _ AU X_I N 9
(M _ AU X_I O1)
LVDS _ AU X_I N11
(M _ AU X_I O 5 )
T
rigger
Contro
ll
er
1
MU
X
TTL _ AU X_I O _ 22
(M 2) _ AU X_I O
OPTO _ AU X_I N24
(M 0) _ AU X_I O
T
rigger
Contro
ll
er
2
T
rigger
Contro
ll
er
3
MU
X
TTL _ AU X_I O _ 12
(M _ AU X_I O8)
T
rigger
Contro
ll
er
0
MU
X
TTL _ AU X_I O _ 13
(M 9 ) _ AU X_I O
T
rigger
Contro
ll
er
1
MU
X
TTL _ AU X_I O _ 14
(M 3) _ AU X_I O
T
rigger
Contro
ll
er
3
MU
X
OPTO _ AU X_I N 9
(M 1) _ AU X_I O
LVDS _ AU X_I N11
(M 5 ) _ AU X_I O
TTL _ AU X_I O _ 6
(M _ AU X_I O2)
MU
X
OPTO _ AU X_I N8
(M _ AU X_I O0)
LVDS _ AU X_I N10
(M _ AU X_I O4)
PSG 2 PSG 3
TTL _ AU X_I O _ 20
(M 8) _ AU X_I O
OPTO _ AU X_I N16
(M 6) _ AU X_I O
LVDS _ AU X_I N18
(M 10) _ AU X_I O
T
rigger
Contro
ll
er
0
MU
X
TTL _ AU X_I O _ 21
(M 9 ) _ AU X_I O
OPTO _ AU X_I N1 7
(M 7 ) _ AU X_I O
LVDS _ AU X_I N1 9
(M 11) _ AU X_I O
LVDS _ AU X_I N26
(M 4) _ AU X_I O
T
rigger
Contro
ll
er
2
MU
X
TTL _ AU X_I O _ 30
(M 3) _ AU X_I O
OPTO _ AU X_I N2 5
(M 1) _ AU X_I O
LVDS _ AU X_I N2 7
(M 5 ) _ AU X_I O
T
rigger
Contro
ll
er
3
MU
X
TTL _ AU X_I O _ 28
(M 8) _ AU X_I O
T
rigger
Contro
ll
er
0
MU
X
TTL _ AU X_I O _ 2 9
(M 9 ) _ AU X_I O
T
rigger
Contro
ll
er
1
MU
X
TTL _ AU X_I O _ 30
(M 3) _ AU X_I O
T
rigger
Contro
ll
er
3
MU
X
OPTO _ AU X_I N2 5
(M 1) _ AU X_I O
LVDS _ AU X_I N2 7
(M 5 ) _ AU X_I O
TTL _ AU X_I O _ 22
(M 2) _ AU X_I O
T
rigger
Contro
ll
er
2
MU
X
OPTO _ AU X_I N24
(M 0) _ AU X_I O