Matrox Radient eCL-DF, Installation And Hardware Reference, Page: 56 / 96

56 Chapter 4: Matrox Radient eCL hardware reference
FPGA chip
The Processing FPGA on Matrox Radient eCL is implemented using a highly
customizable, Altera Stratix III or IV FPGA, with core clock of up to 133 MHz.
Depending on your application requirements, you can purchase the board with
one of the following six supported FPGA chips.
Memory
Matrox Radient eCL can have two types of on-board memory:
• Main on-board memory. This memory is always present and is used to store
acquired images and images for or resulting from processing. As main on-board
memory, Matrox Radient eCL uses 2 Gbytes of DDR2-667 SDRAM. Main
on-board memory is accessed through the memory controller of the Processing
FPGA. The memory controller has multiple input ports and a data transfer rate
of up to 10.6 Gbytes/sec.
• Dedicated Processing FPGA memory (optional). This memory is optional and
is used to store intermediate data while the Processing FPGA performs operations.
As Processing FPGA memory, Matrox Radient eCL uses 4 banks of QDR-II
SRAM that total 16 or 32 Mbytes of memory and have a total transfer rate of up
to 4.0 Gbytes/sec in each direction.
Use the MIL-Lite functions MbufAlloc1d() , MbufAlloc2d() , and
MbufAllocColor() to allocate buffers explicitly in this memory. If you allocate the
buffers with the M_ON_BOARD attribute, they are allocated in main on-board
memory; if you allocate them with the
M_FPGA_ACCESSIBLE + M_FAST_MEMORY attributes, the buffers are
allocated in dedicated Processing FPGA memory.
Altera Stratix III package (744 I/Os) Altera Stratix IV package (744 I/Os)
C4 speed grade C4 speed grade
EP3SL150 EP3SL200 EP3SL340 EP3SE110 EP3SE260 EP4SE530 EP4SE820
Equivalent Logic Elements 142,500 200,000 337,500 107,500 255,000 531,200 813,050
Maximum 18x18
multipliers
384 576 576 896 768 1,024 960
M9K memory blocks 355 468 1,040 639 864 1,280 1610
M144K memory blocks 16 36 48 16 48 64 60