Matrox CronosPlus, Installation And Hardware Reference

Page: 25 / 48

User bits 25
• Level-sensitive "continuous" acquisition: The PCI bus master interface grabs
continuously while the level of the trigger is high/low.
❖
The polarity of the active and inactive levels of the trigger signal is software
programmable.
The trigger signal’s negative component (OPTOTRIG-) is usually connected to
the ground of the trigger source.
User bits
Matrox CronosPlus supports 3 user input signals and can generate 4 user output
signals, to allow you to control external events such as a strobe light. Both input
and output signals are TTL compatible. One user input can generate an interrupt.
These user signals (user bits) are programmed using the MIL-Lite function
MdigControl() . For information on the user bits electrical specifications, see the
section Electrical specifications in Appendix B.
PCI interface
Matrox CronosPlus has a 32-bit PCI bus interface, which is capable of a peak
transfer rate of 132 Mbytes/sec, and operates at 33 MHz.
Matrox CronosPlus uses an internal FIFO to buffer image data while waiting to
access the PCI bus. This helps prevent loss of image data during long bus-access
latencies found in heavily loaded systems. When the PCI bus is extremely loaded,
Matrox CronosPlus might not be able to empty the FIFO when required. This
problem causes an acquisition error known as a "Acquisition error: Data transfer
error (FIFO overflow)". A way to reduce the occurrence of this error is to grab
into a YUV16 packed buffer instead of a BGR24 or BGR32 buffer. In addition,
using an AGP graphics board for display instead of a PCI graphics board will also
reduce the PCI load. For more information, see the subsection titled,
Grabbing
Problems , in Appendix A: Troubleshooting .