MagnaChip MC80C0104, User Manual, Page: 72 / 126

MC80F0104/0204 Preliminary
68 Mar. 2005 Ver 0.2
Serial I/O Mode Register (SIOM) controls serial I/O func-
tion. According to SCK1 and SCK0, the internal clock or
external clock can be selected. Serial I/O Data Register (SIOR) is an 8-bit shift register.
First LSB is send or is received.
Figure 15-2 SIO Control Register
15.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of
SIOM) to “1”. After one cycle of SCK, SIOST is cleared
automatically to “0”. At the default state of POL bit clear,
the serial output data from 8-bit shift register is output at
falling edge of SCLK, and input data is latched at rising edge of SCLK pin (Refer to Figure 15-3 ). When transmis-
sion clock is counted 8 times, serial I/O counter is cleared
as ‘0”. Transmission clock is halted in “H” state and serial
I/O interrupt (SIOIF) occurred.
BTCL
7 6 5 4 3 2 1 0
IOSW POL
SIOST
Serial transmission status bit
Serial transmission Clock selection
INITIAL VALUE: 0000 0001
B
ADDRESS: 0E2
H
SIOM
SIOSF
Serial Input Pin Selection bit
0: SI Pin Selection
1: SO Pin Selection
R/W R/W R/W R/W R/W R
00: f
XIN
÷
4
01: f
XIN
÷
16
10: TMR0OV(Timer0 Overflow)
11: External Clock
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
SCK1 SCK0 SM1 SM0
R/W
Serial transmission Operation Mode
00: Normal Port(R42,R43,R44)
01: Sending Mode(SCK,R43,SO)
10: Receiving Mode(SCK,SI,R44)
11: Sending & Receiving Mode(SCK,SI,SO)
INITIAL VALUE: Undefined
ADDRESS: 0E3
H SIOR
BTCL
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W
R/W
R/W
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
R/W