MagnaChip MC80C0104, User Manual, Page: 43 / 126

Preliminary MC80F0104/0204
Mar. 2005 Ver 0.2 39
11. BASIC INTERVAL TIMER
The MC80F0104/0204 has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown
in Figure 11-1 . In addition, the Basic Interval Timer gen-
erates the time base for watchdog timer counting. It also
provides a Basic interval timer interrupt (BITIF).
The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. As the
count overflow from FFH to 00H, this overflow causes the
interrupt to be generated.
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2. If the RCWDT
bit is set to “1”, the clock source of the BITR is changed to
the internal RC oscillation.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and ad-
dress 0F2
H
is read as a BITR, and written to CKCTLR.
Note:
All control bits of Basic interval timer are in CKCTLR reg-
ister which is located at same address of BITR (address EC
H
). Ad-
dress EC
H
is read as BITR, written to CKCTLR. Therefore, the
CKCTLR can not be accessed by bit manipulation instruction.
Figure 11-1 Block Diagram of Basic Interval Timer
MUX
Basic Interval
BITR
Select Input clock 3
Basic Interval Timer
source
clock
8-bit up-counter
BCK[2:0]
BTCL
÷
1024
÷
512
÷
256
÷
128
÷
64
÷
32
÷
16
÷
8
To Watchdog timer (WDTCK)
CKCTLR
clear
overflow
Internal bus line
clock control register
[0F2
H
]
[0F2
H
]
BITIF
Read
X
IN
PIN
Pr
es
ca
ler
Timer Interrupt
Internal RC OSC
RCWDT
1
0
RCWDT