Macronix MX25L4006E, Manual

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.
- Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from
data change.
Table 2. Protected Area Sizes
Status bit
Protect level 4Mb
BP2 BP1 BP0
0 0 0 0 (none) None
0 0 1 1 (1 block) Block 7
0 1 0 2 (2 blocks) Block 6-7
0 1 1 3 (4 blocks) Block 4-7
1 0 0 4 (8 blocks) All
1 0 1 5 (All) All
1 1 0 6 (All) All
1 1 1 7 (All) All