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12
User’s Guide
Clocks, Cables and Termination
Termination and Word Clock Drive Levels
Unlike AES-3, AES-11, and S/PDIF, there are no published standards
for word clock. While over the years certain common word clock circuit
design practices have emerged, compatibility between manufacturers
is not guaranteed in all cases. Some devices do not have sufficient
output voltage to drive a properly terminated word clock input, while
others require an unusually high input signal voltage to work properly.
When two such devices are mated the result is that the receiving device
may intermittently lose lock or simply not lock at all. The GENx192 was
designed to be compatible with all equipment on the market today.
For ideal word clock transmission conditions to exist, the end of
the cable must be ‘terminated’ with a load impedance that exactly
matches the cable impedance (75Ω.) “Ringing” occurs at the clock
input when there is an impedance mismatch, adding jitter to the signal.
Many devices are by default internally terminated with a 75Ω resistor;
others are either user selectable (through a switch or jumper), or are
completely unterminated. Consult the operator’s manual for each piece
of equipment to determine the word clock input impedance. AES and
S/PDIF do not have these termination issues – properly designed AES
and S/PDIF circuits should be correctly terminated already.
For point to point connections (such as in a star configuration), the
word clock input should always be terminated. If the device at the end
of the cable cannot be internally terminated, then an external 75Ω BNC
terminator and BNC-T connector must be installed.
In a parallel configuration only the device at the end of the cable should
be terminated, and all devices in the middle must be unterminated
(high-impedance). A ‘double-termination’ condition results when two
devices on the same clock leg are terminated. This results in drastically
lower clock voltage, and one or more of the units may fail to lock to the
clock.
Interfacing to Analog Systems
Even today where the significant majority of recording and playback
systems are digital, it is still necessary in certain production
environments to synchronize the playback of analog systems such as
VTR and multitrack tape machines to digital systems that require clock
synchronization. In the digital domain, word clock and AES-3/11 are
used as timing references, whereas in the analog domain video signals
are commonly used.
To synchronize a VTR or analog multitrack to a digital system it is
necessary to use a video blackburst signal as the master timing
reference. Blackburst is typically distributed from a single ‘house sync’
or stand-alone blackburst generator. Most digital systems do not have
video sync inputs. It is therefore necessary to use a second clocking
device that can receive a video signal and output a ‘resolved’ digital
sample clock that can be distributed through a device such as the
GENx192 to all the digital equipment that requires it; a few generators
can output both blackburst and resolved sample clock signals. These
resolvers work as synchronization ‘gearboxes’ by mathematically
relating the video signal to the sample clock. For example, a resolver
can generate a 48 kHz sample clock from a 30 Hz video signal by
outputting (48,000/30) = 1600 samples for every video frame.
Some DAWs and MDMs have video sync inputs as well as clock inputs.
It is acceptable to use the video sync inputs on these devices in lieu
of clock ONLY when using analog inputs and outputs exclusively, AND
when phase-coherent audio is NOT distributed between the video
synchronized devices(s) and other devices in the system. In all other
cases, a valid clock system must be used, particularly when using
digital inputs and outputs. The reason for this is that in most video
resolving circuits, although the video frame rate can be adequately
resolved to the sample clock rate, the phase alignment between
the video and clock signals is arbitrary. Therefore, if two devices are
interconnected digitally but both resolved to black burst, the clock
alignment will be arbitrary and may cause misclocking.
