Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Timer April 1998
12-2
DRAFT COPY
Lucent Technologies Inc.
12.2 Programmable Features and Operation
Three control registers are involved in the operation of the timer. They are the timerc register, the timer0 register,
and the inc register.
12.2.1 timerc Register Encoding
Table 12-1. timerc Register
Bit 15—7 6 5 4 3—0
Field Reserved DISABLE RELOAD T0EN PRESCALE
Field and Value Action
DISABLE = 0 Clocks enabled
DISABLE = 1 Timer clocks of
RELOAD = 0 Count down and stop
RELOAD = 1 Repeat count cycle
T0EN = 0 Hold current count
T0EN = 1 Count toward zero
Prescale
Field
Frequency of
Interrupts
†
† CKO = free-running non-wait-stated clock.
Period at
CKI = 16.67 ns (60 MHz)
(2x Clock)
Period at
CKI
‡
= 25 ns (40 MHz)
(1x Clock)
‡ The DSP1627/28/29 period is based on the internal clock selected (PLL, CKI, or ring oscillator).
0000 CKO/2 66.7 ns 50 ns
0001 CKO/4 133.3 ns 100 ns
0010 CKO/8 266.7 ns 200 ns
0011 CKO/16 533.3 ns 400 ns
0100 CKO/32 1.067
µ
s 800 ns
0101 CKO/64 2.133
µ
s 1.6
µ
s
0110 CKO/128 4.267
µ
s 3.2
µ
s
0111 CKO/256 8.533
µ
s 6.4
µ
s
1000 CKO/512 17.07
µ
s 12.8
µ
s
1001 CKO/1024 34.13
µ
s 25.6
µ
s
1010 CKO/2048 68.27
µ
s 51.2
µ
s
1011 CKO/4096 136.5
µ
s 102.4
µ
s
1100 CKO/8192 273.1
µ
s 204.8
µ
s
1101 CKO/16384 546.1
µ
s 409.6
µ
s
1110 CKO/32768 1.092 ms 819.2
µ
s
1111 CKO/65536 2.185 ms 1.6384 ms