LSI Symbios SYM53C040, Technical Manual

Page: 44 / 214

2-28 Functional Description
2.10.1.1 Interrupt Status Register ( 0xFE04 )
The bits in this register are set when the corresponding interrupt
condition occurs. They are cleared when the interrupt is cleared by the
microcontroller. The register contains interrupt bits for the two SFF-8067
ports or MPIO3_[1:0]; the two programmable timers; the DMA core; the
Two-Wire Serial interfaces; and the SCSI core.
Table 2.5 Register Bits for Interrupt Handling
Register Bit
Location Register or Bit
Name
Function
0xFE04 Interrupt Status Reports to the microcontroller which block asserted the interrupt.
Individual bits in this register may be written to force an interrupt
on the corresponding bit. Refer to the register description for
complete information.
0xFE0D Interrupt Mask Clearing individual bits in this register masks the corresponding
interrupts in the
Interrupt Status (ISR) register from being sent
to the microcontroller.
0xFE0E Interrupt
Destination The bits in this register can be set or cleared to route interrupts
to either of the two interrupt sources to the microcontroller core.
0xFC05, bit 7 End of DMA
Transfer This bit is set when the DMA transfer is complete.
0xFC02, bit 4 Enable Parity
Interrupt When set, causes an interrupt from the SCSI core to occur if a
parity error is detected. The Enable Parity Checking bit must
also be set.
0xFC02, bit 2 Monitor Busy When set, causes an interrupt from the SCSI core to be
generated for an unexpected loss of BSY/.
0xFC07 (Read
register) Reset
Parity/Interrupt
Register Any read to this register resets the Interrupt Request Active bit
(0xFC05, bit 4).
0xFC10, bit 1 DMA Interrupt
Enable When set, the DMA function will generate an interrupt whenever
the TIP bit (bit 0) transitions from 1 to 0. This signifies that the
transfer completed normally, or was interrupted.
0xFC14, bit 0 DMA Interrupt This is the interrupt value for the DMA function. This interrupt will
only be enabled if the IEN bit (bit 1 in register 0xFC10) is set.