LSI LSI53C896, Technical Manual

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5-18 SCSI SCRIPTS Instruction Set
DMA Next Address (DNAD) register. Manually set the
LSI53C896 to the initiator mode if it is reselected, or to
the target mode if it is selected.
If the Select with SATN/ field is set, the SATN/ signal is
asserted during the selection phase.
Wait Disconnect Instruction
The LSI53C896 waits for the target to perform a “legal”
disconnect from the SCSI bus. A “legal” disconnect
occurs when SBSY/ and SSEL/ are inactive for a
minimum of one Bus Free delay (400 ns), after the
LSI53C896 receives a Disconnect Message or a
Command Complete Message.
Wait Reselect Instruction
If the LSI53C896 is selected before being reselected, it
fetches the next instruction from the address pointed to
by the 32-bit jump address field stored in the
DMA Next
Address (DNAD) register. Manually set the LSI53C896 to
the target mode when it is selected.
If the LSI53C896 is reselected, it fetches the next
instruction from the address pointed to by the
DMA
SCRIPTS Pointer (DSP) register.
If the CPU sets the SIGP bit in the Interrupt Status Zero
(ISTAT0) register, the LSI53C896 aborts the Wait
Reselect instruction and fetches the next instruction from
the address pointed to by the 32-bit jump address field
stored in the
DMA Next Address (DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
SCSI Output Control Latch
(SOCL) register are set. When the target bit is set, the
corresponding bit in the SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the ALU is set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output
Control Latch (SOCL) register. When the target bit is
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