LSI LSI53C1000, Technical Manual

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Parallel ROM Interface 2-59
2.3 Parallel ROM Interface
The LSI53C1000 supports up to 1 Mbyte of external memory in binary
increments from 16 Kbytes to allow the use of expansion ROM for
add-in PCI cards. This interface is designed for low-speed operations
such as downloading instruction code from ROM; it is not intended for
dynamic activities such as executing instructions.
System requirements include the LSI53C1000, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 K
Ω
pull-up resistors on the MAD bus require HC
or HCT external components to be used. Pull-up resistors on the 8-bit
bidirectional memory bus at power-up determine the memory size and
speed. The LSI53C1000 senses this bus shortly after the release of the
Reset signal and configures the Expansion ROM Base Address register
and the memory cycle state machines for the appropriate conditions.
The LSI53C1000 supports a variety of sizes and speeds of expansion
ROM. An example set of interface drawings is in
Appendix B, “External
Memory Interface Diagram Examples.” The encoding of pins MAD[3:1]
allows the user to define how much external memory is available to the
LSI53C1000.
Table 2.7 shows the memory space associated with the
possible values of MAD[3:1]. The MAD[3:1] pins are fully described in
Chapter 3, “Signal Descriptions.”