LSI LSI53C1000, Technical Manual

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4-74 Registers
•
An illegal Force CRC Request Block Move is
executed.
•
A SCRIPTS RAM parity error.
Note: The Shadowed SCSI SGE Status 0 register indicates which
condition caused an SGE SCSI interrupt. This register is
shadowed behind the
SCSI Interrupt Status Zero (SIST0)
register. It can be accessed by setting bit 7, the Enable
Shadowed SGE Register (ShSGE) bit, in the
Chip Control
Two (CCNTL2) register.
UDC Unexpected Disconnect 2
This bit is set when the LSI53C1000 is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid
when the LSI53C1000 operates in the initiator mode.
When the LSI53C1000 operates in the low level mode,
any disconnect causes an interrupt, even a valid SCSI
disconnect. This bit is also set if a selection time-out
occurs. Since a selection time-out is not considered an
expected disconnect, an unexpected disconnect may
occur before, at the same time, or stacked after the STO
interrupt.
RST SCSI RST/ Received 1
This bit is set when the LSI53C1000 detects an active
SRST/ signal, whether the reset is generated external to
the chip or caused by the Assert SRST/ bit in the
SCSI
Control One (SCNTL1) register. This SCSI reset
detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SRST/ signal.
PAR Parity/CRC/AIP Error 0
This bit indicates the LSI53C1000 detected a
Parity/CRC/AIP error while receiving or sending SCSI
data. See the Disable Halt on Parity/CRC/AIP Error or
ATN/ condition bit in the
SCSI Control One (SCNTL1)
register for more information about when this condition
will actually be raised.