LSI Logic Confidential
Video Control Register
11-15
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
interrupt handler. The GoO bit remains set while there is
at least one video output transfer outstanding to allow
software polling of completion. Clearing this bit is ignored.
Output data, SAV and EAV are generated even if echo is
not active and the GoO bit is not set.
Video Status Register
Cbus Address: 0xC40004
Read/write
0x200000
ZYO
22
If set (zero Y offset), Y and RGB are assumed to have
the same offset in YUV->RGB and RGB->YUV color
space conversions. If clear, a Y value of 16 corresponds
to an RGB value of zero. Changes to this bit will take
effect at the beginning of the next output field.
OT
21
If set, the video channel output pins (VO_D[15:0]) are
3-stated, independent of any active output transfer. If
clear, these pins are driven by DoMiNo. 3-tating allows
other video sources to share the video output bus. At
reset, this bit is set to avoid contention on the output pins.
The reset sequence can clear this bit if DMN-8600 is the
only driver. This bit should not be changed while an
output transfer is active or pending.
YFirst
20
If set, the video capture or output interleave order is (Y,
CB, Y, CR); otherwise, it is (CB, Y, CR, Y). This bit should
not be changed while an input or output transfer is active
or pending. Changes to this bit take effect on the output
at the beginning of the next output field.
OSync
19
If set when ProgIn is clear, video output of the last byte
of an EAV sequence where the F-bit toggles LOW in (the
31
23
22
21
20
19
18
17
16
Reserved
ZYO
OT
YFirst
OSync
0
Oclkr ISpol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Stop
P-In P-Out
0
Out16
0
Early2 RLEerr VSP
Res SSAV O-Odd
Res
IOdd Early BOvr