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Godson 3A2000 / 3B2000 Processor User Manual
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
4 Shared Cache (SCache)
The SCache module is a three-level cache shared by all processor cores within the Loongson 3A2000 processor. SCache module
The main features include:
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Using 128-bit AXI interface.
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16 items Cache access queue.
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Keywords first.
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Fastest 12 beats from receiving a read invalid request to returning data.
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Support Cache consistency protocol through the directory.
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It can be used for on-chip multi-core structure, and can also be directly connected with single processor IP.
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The 16-way group connection structure is adopted.
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Support ECC check.
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Support DMA consistent read and write and prefetch reading.
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Support 16 kinds of shared cache hashes.
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Support sharing cache by window lock.
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Ensure that read data returns atomicity.
Shared Cache module includes shared Cache management module scachemanage and shared Cache access module
scacheaccess. The Scachemanage module is responsible for processor access requests from the processor and DMA, and shared cache
The TAG, directory and data are stored in the scacheaccess module. In order to reduce power consumption, Cache TAG,
The directory and data can be accessed separately. The shared Cache status bit and w bit are stored with the TAG, and the TAG is stored in the TAG RAM
In, the directory is stored in DIR RAM, and the data is stored in DATA RAM. Invalid request to access shared cache and read at the same time
Get out the TAGs and directories of all roads, and select the directories according to TAG, and read the data according to the hits. Replace request, re
The fill request and write back request only operate the TAG, directory and data along the way.
In order to improve the performance of some specific computing tasks, the shared cache adds a lock mechanism. Shares that fall in the locked area
The Cache block will be locked, so it will not be replaced by the shared Cache (unless the 16-way shared Cache is locked
Piece). Through the chip configuration register space, four groups of lock window registers in the shared Cache module can be dynamically configured
However, it must be ensured that one of the 16 shared caches is not locked. The size of each group of windows can be based on
Make adjustments, but not more than 3/4 of the entire shared cache size. In addition, when the shared cache receives the DMA write request,
If the written area hits and is locked in the shared cache, the DMA write will be written directly to the shared cache instead of
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