4/29/2020
Godson 3A2000 / 3B2000 Processor User Manual
126
Page 168
Godson 3A2000 / 3B2000 Processor User Manual Part 1
When the Uncache request occurs, the contents of the store fill buffer have been written back to the Cache; the second is that all
The unlock operation in the synchronous operation shared between different cores is implemented using LL / SC instructions;
8. Do not use the MSI function of the device. When you must use the MSI function, you need to transfer the data of the POST channel of the HT controller
Set the number of receive buffers to 1 and reconnect to the HT bus;
9. Lock Cache operations cannot be used for DMA areas where hardware automatically maintains consistency.
Modifications that can also be used to improve performance are:
1. Increase support for FTLB;
2. Add support for TLB fast refill;
3. Add wait instruction support;
4. Add prefetch instruction support;
5. Use DI / EI to implement interrupt return. But it should be noted that the [31: 4] returned by the EI instruction is a random value, which is different from the MIPS
Differences.
13.5 Other changes
1. The performance counter overflow interrupt cannot achieve precise interrupts, resulting in restrictions on the current perf tools. If needed
To do so, frequent mfc0 perfcnt instructions must be added (user mode is available), for example, in the processing function of high-frequency clock interrupt
Insert the instruction in the data, but it will still cause the interruption to not be generated in time, and the event statistical error will be larger;
164