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Godson 3A2000 / 3B2000 Processor User Manual
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2. After the CPU is powered on, close the Store Fill Buffer of all cores;
3. Immediately after the CPU is powered on, turn off the word write merge function of all cores;
4. If you need to maintain compatibility with 3A5, set the PRID hidden bit in the CP0 Diag register of all cores;
5. Modify the statements of jr rx and rx which are not register 31 in all assembly codes to jr $ 31;
6. Use code similar to 3B1500 to configure processor core, memory and node PLL;
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7. Use the memory controller configuration and parameter training code similar to 3B1500;
8. If HT works in 1.0 mode, HT can only work in 8-bit mode;
9. If an SPI controller is used, the base address is changed from 0xBFE001F0 to 0xBFE00220;
In addition to these necessary changes, the following changes can be made to enhance the PMON function:
1. Modify the delay delay of the buzzer to ensure that the user can hear the buzzer;
2. Add support to shut down the defective core clock;
13.4 Guidelines for kernel changes
The modifications required in the kernel include:
1. Modify the Cache description structure in the kernel. Both VCache and SCache are connected using 16-way groups;
2. Modify the calculation method of the temperature sensor, which is the same as 3B1500 with the readout value -100. At present, the samples have not been tested and calibrated,
There may be a large deviation between the read value of some chips and the actual temperature, so it is recommended that in the current kernel, temporarily
Do not use the temperature indication of the internal temperature sensor of the processor;
3. Modify the configuration register address when shutting down the core;
4. Change the operation of flashing ICache / DCache to flashing ICache / DCache / VCache;
5. If an SPI controller is used, the base address is changed from 0xBFE001F0 to 0xBFE00220;
6. Uncache DMA must be used, and data consistency of Cache must be maintained by software;
7. Add store fill buffer support: One is to add a SYNC before all Uncache requests to ensure
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