57
Rev. B
APPLICATIONS INFORMATION
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, there is plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pull-
up and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time is:
R
PULLUP
=
t
RISE
3•100pF
=
1k
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one time constant. The
SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
R
PULLUP
=
2µs– 500ns
3•100pF
=
5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and deter-
mine if the RC time constant is too long for the applica-
tion. If possible reduce the parasitic capacitance. If not,
reduce the pull-up resistor sufficiently to assure proper
timing. The SHARE_CLK pull-up resistor has a similar
equation with a period of 10µs and a pull-down time of
1µs. The RC time constant should be approximately 3µs
or faster.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4680 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_ CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
200kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the
ALERT
pin is
pulled low. The fault can be cleared by writing a 1 to the
bit. If the user does not wish to see the
ALERT
pin assert
if a PLL_FAULT occurs, the SMBALERT_MASK command
can be used to prevent the alert.
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if multiple parts share the SYNC pins
and the signal is not clocking, the parts will not be syn-
chronized and excess voltage ripple on the output may be
present. Bit 10 of MFR_PADS will be asserted low if this
condition exists.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
