LTC3350
28
3350fc
For more information
www.linear.com/LTC3350
applicaTions inForMaTion
Because supercapacitors have low series resistance, it is
important that C
CAP
be sized properly so that the bulk of
the inductor current ripple flows through the filter capaci-
tor and not the supercapacitor. It is recommended that:
1
8C
CAP
•
f
SW
+
R
ESR
⎛
⎝⎜
⎞
⎠⎟
≤
n
•
R
SC
5
where n is the number of supercapacitors in the stack and
R
SC
is the ESR of each supercapacitor. The capacitance
on VCAP can be a combination of bulk and high frequency
capacitors. Aluminum electrolytic, OS-CON and POSCAP
capacitors are suitable for bulk capacitance while multilayer
ceramics are recommended for high frequency filtering.
Power MOSFET Selection
Two external power MOSFETs must be selected for
the LTC3350’s synchronous controller: one N-channel
MOSFET for the top switch and one N-channel MOSFET
for the bottom switch. The selection criteria of the external
N-channel power MOSFETs include maximum drain-source
voltage (V
DSS
), threshold voltage, on-resistance (R
DS(ON)
),
reverse transfer capacitance (C
RSS
), total gate charge (Q
G
),
and maximum continuous drain current.
V
DSS
of both MOSFETs should be selected to be higher
than the maximum input supply voltage (including
transient). The peak-to-peak drive levels are set by the
DRV
CC
voltage. Logic-level threshold MOSFETs should
be used because DRV
CC
is powered from either INTV
CC
(5V) or an external LDO whose output voltage must be
less than 5.5V.
MOSFET power losses are determined by R
DS(ON)
, C
RSS
and Q
G
. The conduction loss at maximum charge current
for the top and bottom MOSFET switches are:
P
COND(TOP)
=
V
CAP
V
OUT
I
CHG(MAX)
2
•
R
DS(ON)
1
+ δ∆
T
(
)
P
COND(BOT)
=
1–
V
CAP
V
OUT
⎛
⎝⎜
⎞
⎠⎟
I
CHG(MAX)
2
•
R
DS(ON)
1
+ δ∆
T
(
)
The term (1+
δ∆
T) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ
= 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Both MOSFET switches have conduction loss. However,
transition loss occurs only in the top MOSFET in step-
down mode and only in the bottom MOSFET in step-up
mode. These losses are proportional to V
OUT
2
and can
be considerably large in high voltage applications (V
OUT
> 20V). The maximum transition loss is:
P
TRAN
≈
k
2
V
OUT
2
•
I
CHG(MAX)
•
C
RSS
•
f
SW
where k is related to the drive current during the Miller
plateau and is approximately equal to one.
The synchronous controller can operate in both step-down
and step-up mode with different voltages on V
OUT
in each
mode. If V
OUT
is 12V in step-down mode (input power
available) and 10V in step-up mode (backup mode) then
both MOSFETs can be sized to minimize conduction loss. If
V
OUT
can be as high as 25V while charging and V
OUT
is held
to 6V in backup mode, then the MOSFETs should be sized
to minimize losses during backup mode. This may lead to
choosing a high side MOSFET with significant transition
loss which may be tolerable when input power is avail-
able so long as thermal issues do not become a limiting
factor. The bottom MOSFET can be chosen to minimize
conduction loss. If step-up mode is unused, then choosing
a high side MOSFET that that has a higher R
DS(ON)
device
and lower C
RSS
would minimize overall losses.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
Q
G
, must be charged and discharged each switching cycle.
The power is lost to the internal LDO and gate drivers within
the LTC3350. The power lost due to charging the gates is:
P
G
≈ (Q
GTOP
+ Q
GBOT
) •
f
SW
•
V
OUT
where Q
GTOP
is the top MOSFET gate charge and Q
GBOT
is the bottom MOSFET gate charge. Whenever possible,
utilize MOSFET switches that minimize the total gate charge
to limit the internal power dissipation of the LTC3350.
Schottky Diode Selection
Optional Schottky diodes can be placed in parallel with the
top and bottom MOSFET switches. These diodes clamp
SW during the non-overlap times between conduction of
the top and bottom MOSFET switches. This prevents the
